Lines Matching +full:0 +full:x19004
112 .reg = 0x2e020,
120 .reg = 0x2f020,
171 return 0; in clk_cpu_div_set_rate()
214 { 384000000, P_XO, 0xd, 0, 0 },
215 { 413000000, P_XO, 0xc, 0, 0 },
216 { 448000000, P_XO, 0xb, 0, 0 },
217 { 488000000, P_XO, 0xa, 0, 0 },
218 { 512000000, P_XO, 0x9, 0, 0 },
219 { 537000000, P_XO, 0x8, 0, 0 },
220 { 565000000, P_XO, 0x7, 0, 0 },
221 { 597000000, P_XO, 0x6, 0, 0 },
222 { 632000000, P_XO, 0x5, 0, 0 },
223 { 672000000, P_XO, 0x4, 0, 0 },
224 { 716000000, P_XO, 0x3, 0, 0 },
225 { 768000000, P_XO, 0x2, 0, 0 },
226 { 823000000, P_XO, 0x1, 0, 0 },
227 { 896000000, P_XO, 0x0, 0, 0 },
232 .cdiv.reg = 0x2e020,
236 .enable_reg = 0x2e000,
237 .enable_mask = BIT(0),
369 { 0, 15 },
377 .cdiv.reg = 0x2f020,
396 .cdiv.reg = 0x2f020,
415 { P_XO, 0 },
427 F(48000000, P_XO, 1, 0, 0),
428 F(100000000, P_FEPLL200, 2, 0, 0),
433 .cmd_rcgr = 0x21024,
446 .halt_reg = 0x21030,
448 .enable_reg = 0x21030,
449 .enable_mask = BIT(0),
463 { P_XO, 0 },
473 F(48000000, P_XO, 1, 0, 0),
474 F(200000000, P_FEPLL200, 1, 0, 0),
479 .cmd_rcgr = 0x1b000,
493 .halt_reg = 0x1b010,
495 .enable_reg = 0x1b010,
496 .enable_mask = BIT(0),
509 .halt_reg = 0x1b00C,
511 .enable_reg = 0x1b00C,
512 .enable_mask = BIT(0),
530 .cmd_rcgr = 0x200c,
543 .halt_reg = 0x2008,
545 .enable_reg = 0x2008,
546 .enable_mask = BIT(0),
559 .cmd_rcgr = 0x3000,
572 .halt_reg = 0x3010,
574 .enable_reg = 0x3010,
575 .enable_mask = BIT(0),
588 { P_XO, 0 },
604 F(48000000, P_XO, 1, 0, 0),
609 .cmd_rcgr = 0x2024,
623 .halt_reg = 0x2004,
625 .enable_reg = 0x2004,
626 .enable_mask = BIT(0),
639 .cmd_rcgr = 0x3014,
653 .halt_reg = 0x300c,
655 .enable_reg = 0x300c,
656 .enable_mask = BIT(0),
678 F(48000000, P_XO, 1, 0, 0),
683 .cmd_rcgr = 0x2044,
697 .halt_reg = 0x203c,
699 .enable_reg = 0x203c,
700 .enable_mask = BIT(0),
713 .cmd_rcgr = 0x3034,
727 .halt_reg = 0x302c,
729 .enable_reg = 0x302c,
730 .enable_mask = BIT(0),
743 F(1250000, P_FEPLL200, 1, 16, 0),
744 F(2500000, P_FEPLL200, 1, 8, 0),
745 F(5000000, P_FEPLL200, 1, 4, 0),
750 .cmd_rcgr = 0x8004,
764 .halt_reg = 0x8000,
766 .enable_reg = 0x8000,
767 .enable_mask = BIT(0),
780 .cmd_rcgr = 0x9004,
794 .halt_reg = 0x9000,
796 .enable_reg = 0x9000,
797 .enable_mask = BIT(0),
810 .cmd_rcgr = 0xa004,
824 .halt_reg = 0xa000,
826 .enable_reg = 0xa000,
827 .enable_mask = BIT(0),
840 { P_XO, 0 },
853 F(400000, P_XO, 1, 1, 0),
858 F(192000000, P_DDRPLL, 1, 0, 0),
863 .cmd_rcgr = 0x18004,
877 F(48000000, P_XO, 1, 0, 0),
878 F(200000000, P_FEPLL200, 1, 0, 0),
879 F(384000000, P_DDRPLLAPSS, 1, 0, 0),
880 F(413000000, P_DDRPLLAPSS, 1, 0, 0),
881 F(448000000, P_DDRPLLAPSS, 1, 0, 0),
882 F(488000000, P_DDRPLLAPSS, 1, 0, 0),
883 F(500000000, P_FEPLL500, 1, 0, 0),
884 F(512000000, P_DDRPLLAPSS, 1, 0, 0),
885 F(537000000, P_DDRPLLAPSS, 1, 0, 0),
886 F(565000000, P_DDRPLLAPSS, 1, 0, 0),
887 F(597000000, P_DDRPLLAPSS, 1, 0, 0),
888 F(632000000, P_DDRPLLAPSS, 1, 0, 0),
889 F(672000000, P_DDRPLLAPSS, 1, 0, 0),
890 F(716000000, P_DDRPLLAPSS, 1, 0, 0),
895 { P_XO, 0 },
909 .cmd_rcgr = 0x1900c,
923 F(48000000, P_XO, 1, 0, 0),
924 F(100000000, P_FEPLL200, 2, 0, 0),
929 .cmd_rcgr = 0x19014,
942 .halt_reg = 0x19004,
945 .enable_reg = 0x6000,
959 .halt_reg = 0x1008,
962 .enable_reg = 0x6000,
975 .halt_reg = 0x2103c,
977 .enable_reg = 0x2103c,
978 .enable_mask = BIT(0),
992 .halt_reg = 0x1300c,
994 .enable_reg = 0x1300c,
995 .enable_mask = BIT(0),
1008 .halt_reg = 0x16024,
1011 .enable_reg = 0x6000,
1012 .enable_mask = BIT(0),
1024 .halt_reg = 0x16020,
1027 .enable_reg = 0x6000,
1040 .halt_reg = 0x1601c,
1043 .enable_reg = 0x6000,
1056 { P_XO, 0 },
1066 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1071 .cmd_rcgr = 0x12000,
1084 .halt_reg = 0x12010,
1086 .enable_reg = 0x12010,
1087 .enable_mask = BIT(0),
1100 .halt_reg = 0xe004,
1103 .enable_reg = 0x6000,
1116 .halt_reg = 0xe008,
1118 .enable_reg = 0xe008,
1119 .enable_mask = BIT(0),
1131 .halt_reg = 0x1d00c,
1133 .enable_reg = 0x1d00c,
1134 .enable_mask = BIT(0),
1146 .halt_reg = 0x1d004,
1148 .enable_reg = 0x1d004,
1149 .enable_mask = BIT(0),
1161 .halt_reg = 0x1d008,
1163 .enable_reg = 0x1d008,
1164 .enable_mask = BIT(0),
1176 .halt_reg = 0x13004,
1179 .enable_reg = 0x6000,
1192 .halt_reg = 0x1c008,
1194 .enable_reg = 0x1c008,
1195 .enable_mask = BIT(0),
1207 .halt_reg = 0x1c004,
1209 .enable_reg = 0x1c004,
1210 .enable_mask = BIT(0),
1222 .halt_reg = 0x18010,
1224 .enable_reg = 0x18010,
1225 .enable_mask = BIT(0),
1237 .halt_reg = 0x1800c,
1239 .enable_reg = 0x1800c,
1240 .enable_mask = BIT(0),
1253 .halt_reg = 0x5004,
1256 .enable_reg = 0x6000,
1269 .halt_reg = 0x1e00c,
1271 .enable_reg = 0x1e00c,
1272 .enable_mask = BIT(0),
1284 .halt_reg = 0x1e010,
1286 .enable_reg = 0x1e010,
1287 .enable_mask = BIT(0),
1301 F(2000000, P_FEPLL200, 10, 0, 0),
1306 .cmd_rcgr = 0x1e000,
1319 .halt_reg = 0x1e014,
1321 .enable_reg = 0x1e014,
1322 .enable_mask = BIT(0),
1335 .halt_reg = 0x1e028,
1337 .enable_reg = 0x1e028,
1338 .enable_mask = BIT(0),
1350 .halt_reg = 0x1e02C,
1352 .enable_reg = 0x1e02C,
1353 .enable_mask = BIT(0),
1367 .halt_reg = 0x1e030,
1369 .enable_reg = 0x1e030,
1370 .enable_mask = BIT(0),
1383 { P_XO, 0 },
1393 F(48000000, P_XO, 1, 0, 0),
1394 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1399 .cmd_rcgr = 0x1f000,
1413 .halt_reg = 0x1f00C,
1415 .enable_reg = 0x1f00C,
1416 .enable_mask = BIT(0),
1429 .halt_reg = 0x1f00C,
1431 .enable_reg = 0x1f00C,
1432 .enable_mask = BIT(0),
1447 .halt_reg = 0x1f010,
1449 .enable_reg = 0x1f010,
1450 .enable_mask = BIT(0),
1464 { P_XO, 0 },
1474 F(48000000, P_XO, 1, 0, 0),
1475 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1480 .cmd_rcgr = 0x20000,
1493 .halt_reg = 0x2000c,
1495 .enable_reg = 0x2000c,
1496 .enable_mask = BIT(0),
1509 .halt_reg = 0x2000c,
1511 .enable_reg = 0x2000c,
1512 .enable_mask = BIT(0),
1527 .halt_reg = 0x20010,
1529 .enable_reg = 0x20010,
1530 .enable_mask = BIT(0),
1617 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
1618 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
1619 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
1620 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
1621 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1622 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
1623 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
1624 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
1625 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
1626 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
1627 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1628 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
1629 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
1630 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
1631 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
1632 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
1633 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
1634 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
1635 [PCIE_AHB_ARES] = { 0x1d010, 10 },
1636 [PCIE_PWR_ARES] = { 0x1d010, 9 },
1637 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
1638 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
1639 [PCIE_PHY_ARES] = { 0x1d010, 6 },
1640 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
1641 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
1642 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
1643 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
1644 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1645 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
1646 [ESS_RESET] = { 0x12008, 0},
1647 [GCC_BLSP1_BCR] = {0x01000, 0},
1648 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
1649 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
1650 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
1651 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
1652 [GCC_BIMC_BCR] = {0x04000, 0},
1653 [GCC_TLMM_BCR] = {0x05000, 0},
1654 [GCC_IMEM_BCR] = {0x0E000, 0},
1655 [GCC_ESS_BCR] = {0x12008, 0},
1656 [GCC_PRNG_BCR] = {0x13000, 0},
1657 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
1658 [GCC_CRYPTO_BCR] = {0x16000, 0},
1659 [GCC_SDCC1_BCR] = {0x18000, 0},
1660 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
1661 [GCC_AUDIO_BCR] = {0x1B008, 0},
1662 [GCC_QPIC_BCR] = {0x1C000, 0},
1663 [GCC_PCIE_BCR] = {0x1D000, 0},
1664 [GCC_USB2_BCR] = {0x1E008, 0},
1665 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
1666 [GCC_USB3_BCR] = {0x1E024, 0},
1667 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
1668 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
1669 [GCC_PCNOC_BCR] = {0x2102C, 0},
1670 [GCC_DCD_BCR] = {0x21038, 0},
1671 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
1672 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
1673 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
1674 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
1675 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
1676 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
1677 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
1678 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
1679 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
1680 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
1681 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
1682 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
1683 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
1684 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
1685 [GCC_TCSR_BCR] = {0x22000, 0},
1686 [GCC_MPM_BCR] = {0x24000, 0},
1687 [GCC_SPDM_BCR] = {0x25000, 0},
1688 [ESS_MAC1_ARES] = {0x1200C, 0},
1689 [ESS_MAC2_ARES] = {0x1200C, 1},
1690 [ESS_MAC3_ARES] = {0x1200C, 2},
1691 [ESS_MAC4_ARES] = {0x1200C, 3},
1692 [ESS_MAC5_ARES] = {0x1200C, 4},
1693 [ESS_PSGMII_ARES] = {0x1200C, 5},
1700 .max_register = 0x2ffff,
1722 int err = 0; in gcc_ipq4019_cpu_clk_notifier_fn()