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Searched +full:0 +full:x10700 (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dcib.txt26 reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
27 <0x10700 0x0000e100 0x0 0x8>; /* EN */
H A Dciu.txt13 the CIU and may have a value of 0 or 1. The second cell is the bit
14 within the bank and may have a value between 0 and 63.
21 * 1) Controller register (0 or 1)
22 * 2) Bit within the register (0..63)
25 reg = <0x10700 0x00000000 0x0 0x7000>;
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-octeon.txt8 - #size-cells : <0>, also as required by generic SPI binding.
16 reg = <0x10700 0x00001000 0x0 0x100>;
17 interrupts = <0 58>;
19 #size-cells = <0>;
21 eeprom@0 {
23 reg = <0>;
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mix.txt26 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
27 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
28 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
29 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
32 local-mac-address = [ 00 0f b7 10 63 54 ];
/linux/Documentation/devicetree/bindings/gpio/
H A Dcavium,octeon-3860-gpio.yaml51 reg = <0x10700 0x00000800 0x0 0x100>;
57 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
58 <0 20>, <0 21>, <0 22>, <0 23>,
59 <0 24>, <0 25>, <0 26>, <0 27>,
60 <0 28>, <0 29>, <0 30>, <0 31>;
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dtsi12 soc@0 {
22 * 1) Controller register (0 or 1)
23 * 2) Bit within the register (0..63)
26 reg = <0x10700 0x00000000 0x0 0x7000>;
32 reg = <0x10700 0x00000800 0x0 0x100>;
35 * 1) GPIO pin number (0..15)
44 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
45 <0 20>, <0 21>, <0 22>, <0 23>,
46 <0 24>, <0 25>, <0 26>, <0 27>,
47 <0 28>, <0 29>, <0 30>, <0 31>;
[all …]
H A Docteon_3xxx.dts13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
H A Docteon_68xx.dts16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx.h16 #define PCI_DEVID_OCTEONTX2_CGX 0xA059
19 #define PCI_CFG_REG_BAR_NUM 0
21 #define CGX_ID_MASK 0xF
24 #define CGXX_CMRX_CFG 0x00
32 #define CGX_LMAC_TYPE_MASK 0xF
33 #define CGXX_CMRX_INT 0x040
35 #define CGXX_CMR_GLOBAL_CONFIG 0x08
39 #define CGXX_CMRX_INT_ENA_W1S 0x058
40 #define CGXX_CMRX_RX_ID_MAP 0x060
41 #define CGXX_CMRX_RX_STAT0 0x070
[all …]
/linux/drivers/input/joystick/
H A Danalog.c38 module_param_array_named(map, js, charp, &js_nargs, 0);
45 #define ANALOG_RUDDER 0x00004
46 #define ANALOG_THROTTLE 0x00008
47 #define ANALOG_AXES_STD 0x0000f
48 #define ANALOG_BTNS_STD 0x000f0
50 #define ANALOG_BTNS_CHF 0x00100
51 #define ANALOG_HAT1_CHF 0x00200
52 #define ANALOG_HAT2_CHF 0x00400
53 #define ANALOG_HAT_FCS 0x00800
54 #define ANALOG_HATS_ALL 0x00e00
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv515.c47 0,
59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
70 radeon_ring_write(ring, 0); in rv515_ring_start()
71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
72 radeon_ring_write(ring, 0); in rv515_ring_start()
73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]