1*6b52c00fSDavid DaneyCavium, Inc. OCTEON SOC SPI master controller. 2*6b52c00fSDavid Daney 3*6b52c00fSDavid DaneyRequired properties: 4*6b52c00fSDavid Daney- compatible : "cavium,octeon-3010-spi" 5*6b52c00fSDavid Daney- reg : The register base for the controller. 6*6b52c00fSDavid Daney- interrupts : One interrupt, used by the controller. 7*6b52c00fSDavid Daney- #address-cells : <1>, as required by generic SPI binding. 8*6b52c00fSDavid Daney- #size-cells : <0>, also as required by generic SPI binding. 9*6b52c00fSDavid Daney 10*6b52c00fSDavid DaneyChild nodes as per the generic SPI binding. 11*6b52c00fSDavid Daney 12*6b52c00fSDavid DaneyExample: 13*6b52c00fSDavid Daney 14*6b52c00fSDavid Daney spi@1070000001000 { 15*6b52c00fSDavid Daney compatible = "cavium,octeon-3010-spi"; 16*6b52c00fSDavid Daney reg = <0x10700 0x00001000 0x0 0x100>; 17*6b52c00fSDavid Daney interrupts = <0 58>; 18*6b52c00fSDavid Daney #address-cells = <1>; 19*6b52c00fSDavid Daney #size-cells = <0>; 20*6b52c00fSDavid Daney 21*6b52c00fSDavid Daney eeprom@0 { 22*6b52c00fSDavid Daney compatible = "st,m95256", "atmel,at25"; 23*6b52c00fSDavid Daney reg = <0>; 24*6b52c00fSDavid Daney spi-max-frequency = <5000000>; 25*6b52c00fSDavid Daney spi-cpha; 26*6b52c00fSDavid Daney spi-cpol; 27*6b52c00fSDavid Daney 28*6b52c00fSDavid Daney pagesize = <64>; 29*6b52c00fSDavid Daney size = <32768>; 30*6b52c00fSDavid Daney address-width = <16>; 31*6b52c00fSDavid Daney }; 32*6b52c00fSDavid Daney }; 33*6b52c00fSDavid Daney 34