Lines Matching +full:0 +full:x10700

16 #define	PCI_DEVID_OCTEONTX2_CGX		0xA059
19 #define PCI_CFG_REG_BAR_NUM		0
21 #define CGX_ID_MASK			0xF
24 #define CGXX_CMRX_CFG			0x00
32 #define CGX_LMAC_TYPE_MASK		0xF
33 #define CGXX_CMRX_INT			0x040
35 #define CGXX_CMR_GLOBAL_CONFIG          0x08
39 #define CGXX_CMRX_INT_ENA_W1S		0x058
40 #define CGXX_CMRX_RX_ID_MAP		0x060
41 #define CGXX_CMRX_RX_STAT0		0x070
42 #define CGXX_CMRX_RX_LOGL_XON		0x100
43 #define CGXX_CMRX_RX_LMACS		0x128
44 #define CGXX_CMRX_RX_DMAC_CTL0		(0x1F8 + mac_ops->csr_offset)
49 #define CGX_DMAC_BCAST_MODE		BIT_ULL(0)
50 #define CGXX_CMRX_RX_DMAC_CAM0		(0x200 + mac_ops->csr_offset)
53 #define CGXX_CMRX_RX_DMAC_CAM1		0x400
54 #define CGX_RX_DMAC_ADR_MASK		GENMASK_ULL(47, 0)
55 #define CGXX_CMRX_TX_STAT0		0x700
56 #define CGXX_SCRATCH0_REG		0x1050
57 #define CGXX_SCRATCH1_REG		0x1058
58 #define CGX_CONST			0x2000
61 #define CGXX_SPUX_CONTROL1		0x10000
62 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS	0x10700
63 #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS	0x10800
64 #define CGXX_SPUX_RSFEC_CORR		0x10088
65 #define CGXX_SPUX_RSFEC_UNCORR		0x10090
68 #define CGXX_GMP_PCS_MRX_CTL		0x30000
71 #define CGXX_SMUX_RX_FRM_CTL		0x20020
74 #define CGXX_GMP_GMI_RXX_FRM_CTL	0x38028
77 #define CGXX_SMUX_TX_CTL		0x20178
78 #define CGXX_SMUX_TX_PAUSE_PKT_TIME	0x20110
79 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL	0x20120
80 #define CGXX_SMUX_SMAC                        0x20108
81 #define CGXX_SMUX_CBFC_CTL                    0x20218
82 #define CGXX_SMUX_CBFC_CTL_RX_EN             BIT_ULL(0)
87 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME	0x38230
88 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL	0x38248
90 #define CGXX_CMR_RX_OVR_BP		0x130
97 #define DEFAULT_PAUSE_TIME		0x7FF
99 #define CGX_LMAC_FWI			0
107 	LMAC_MODE_SGMII		= 0,