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Searched +full:0 +full:x104c (Results 1 – 25 of 47) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
/freebsd/sys/net80211/
H A Dieee80211_wps.h34 #define IEEE80211_WPS_ATTR_AP_CHANNEL 0x1001
35 #define IEEE80211_WPS_ATTR_ASSOC_STATE 0x1002
36 #define IEEE80211_WPS_ATTR_AUTH_TYPE 0x1003
37 #define IEEE80211_WPS_ATTR_AUTH_TYPE_FLAGS 0x1004
38 #define IEEE80211_WPS_ATTR_AUTHENTICATOR 0x1005
39 #define IEEE80211_WPS_ATTR_CONFIG_METHODS 0x1008
40 #define IEEE80211_WPS_ATTR_CONFIG_ERROR 0x1009
41 #define IEEE80211_WPS_ATTR_CONFIRM_URL4 0x100a
42 #define IEEE80211_WPS_ATTR_CONFIRM_URL6 0x100b
43 #define IEEE80211_WPS_ATTR_CONN_TYPE 0x100c
[all …]
/freebsd/contrib/wpa/src/wps/
H A Dwps_defs.h25 #define WPS_VERSION 0x20
56 ATTR_AP_CHANNEL = 0x1001,
57 ATTR_ASSOC_STATE = 0x1002,
58 ATTR_AUTH_TYPE = 0x1003,
59 ATTR_AUTH_TYPE_FLAGS = 0x1004,
60 ATTR_AUTHENTICATOR = 0x1005,
61 ATTR_CONFIG_METHODS = 0x1008,
62 ATTR_CONFIG_ERROR = 0x1009,
63 ATTR_CONFIRM_URL4 = 0x100a,
64 ATTR_CONFIRM_URL6 = 0x100b,
[all …]
/freebsd/sys/dev/dwc/
H A Ddwc1000_reg.h37 #define MAC_CONFIGURATION 0x0
47 #define MAC_FRAME_FILTER 0x4
53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
54 #define GMAC_MAC_HTHIGH 0x08
55 #define GMAC_MAC_HTLOW 0x0c
56 #define GMII_ADDRESS 0x10
57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
61 #define GMII_ADDRESS_CR_MASK 0xf
64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
H A Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
H A Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
[all …]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
/freebsd/sys/dev/firewire/
H A Dfwohcireg.h38 #define PCI_CBMEM PCIR_BAR(0)
40 #define FW_VENDORID_NATSEMI 0x100B
41 #define FW_VENDORID_NEC 0x1033
42 #define FW_VENDORID_SIS 0x1039
43 #define FW_VENDORID_TI 0x104c
44 #define FW_VENDORID_SONY 0x104d
45 #define FW_VENDORID_VIA 0x1106
46 #define FW_VENDORID_RICOH 0x1180
47 #define FW_VENDORID_APPLE 0x106b
48 #define FW_VENDORID_LUCENT 0x11c1
[all …]
/freebsd/sys/dev/hdmi/
H A Ddwc_hdmireg.h29 #define HDMI_DESIGN_ID 0x0000
30 #define HDMI_REVISION_ID 0x0001
31 #define HDMI_PRODUCT_ID0 0x0002
32 #define HDMI_PRODUCT_ID1 0x0003
35 #define HDMI_IH_FC_STAT0 0x0100
36 #define HDMI_IH_FC_STAT1 0x0101
37 #define HDMI_IH_FC_STAT2 0x0102
38 #define HDMI_IH_AS_STAT0 0x0103
39 #define HDMI_IH_PHY_STAT0 0x0104
40 #define HDMI_IH_PHY_STAT0_HPD (1 << 0)
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_fpga.txt34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
H A Dt5fw_cfg_fpga.txt49 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
84 reg[0x59c4] = 0x3/0x3 # enable the timers
103 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
104 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
105 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
106 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
107 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
108 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
109 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
110 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
[all …]
H A Dt5fw_cfg_uwire.txt34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
H A Dt6fw_cfg_uwire.txt34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
H A Dt4fw_cfg_uwire.txt49 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
96 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
97 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
98 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
99 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
100 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
101 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
102 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
103 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
104 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
/freebsd/sys/dev/e1000/
H A De1000_hw.h44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_radar.c33 #define AR9300_DFS_RRSSI 0
48 * for register 0x1040 to 0x104c
50 #define AR9300_DEFAULT_DIFS 0x002ffc0f
61 {30, 2, 300, 400, 2, 30, 3, 0, 5, 15, 0, 0, 1, 31}, /* Type 5*/
63 {30, 2, 400, 1200, 2, 30, 7, 0, 5, 15, 0, 0, 0, 32}, /* Type 6 */
67 {10, 5, 200, 400, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* Type 1 */
68 {10, 5, 400, 600, 0, 24, 5, 0, 8, 15, 0, 0, 2, 37}, /* Type 1 */
69 {10, 5, 600, 800, 0, 24, 5, 0, 8, 15, 0, 0, 2, 38}, /* Type 1 */
70 {10, 5, 800, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 39}, /* Type 1 */
71 // {10, 5, 200, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33},
[all …]
/freebsd/sys/dev/bhnd/
H A Dbhnd_ids.h47 * [11:8 ][7:0 ]
53 * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations
54 * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B).
56 #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */
57 #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */
58 #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */
59 #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */
66 #define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */
69 #define PCI_VENDOR_ASUSTEK 0x1043
70 #define PCI_VENDOR_EPIGRAM 0xfeda
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DUCS@SIP%CNS11643-4.src5 SRC_ZONE 0x0057 - 0xFA1C
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x0057 = 0x4F7C
48 0x0065 = 0x2156
49 0x0086 = 0x2121
50 0x00A2 = 0x2226
51 0x00A3 = 0x2225
52 0x00F1 = 0x2624
53 0x010E = 0x2128
[all …]

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