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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-clock.yaml58 reg = <0x10010000 0x30000>;
H A Dsamsung,exynos7885-clock.yaml168 reg = <0x10010000 0x8000>;
/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml61 reg = <0x10010000 0x1000>;
/linux/Documentation/devicetree/bindings/input/
H A Dmediatek,mt6779-keypad.yaml83 reg = <0 0x10010000 0 0x1000>;
/linux/Documentation/devicetree/bindings/pci/
H A Dst,stm32-pcie-host.yaml37 '^pcie@[0-2],0$':
81 reg = <0x48400000 0x400000>,
82 <0x10000000 0x10000>;
85 interrupt-map-mask = <0 0 0 7>;
86 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
87 <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
88 <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
89 <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
92 ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
93 <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
188 <&cpu0_intc 0xffffffff>,
189 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
190 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
191 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
59 reg = <0x1>;
86 reg = <0x2>;
113 reg = <0x3>;
140 reg = <0x4>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
38 #size-cells = <0>;
40 port@0 {
41 reg = <0>;
71 reg = <0x10000000 0x200>;
72 ranges = <0x0 0x10000000 0x200>;
76 led@8,0 {
78 reg = <0x08 0x04>;
79 offset = <0x08>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
[all …]
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dni.c70 0x98fc,
71 0x98f0,
72 0x9834,
73 0x9838,
74 0x9870,
75 0x9874,
76 0x8a14,
77 0x8b24,
78 0x8bcc,
79 0x8b10,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmCC_BIF_BX_FUSESTRAP0 0x14D7
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
H A Dbif_5_0_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmCC_BIF_BX_FUSESTRAP0 0x14D7
31 #define mmCC_BIF_BX_STRAP2 0x152A
32 #define mmBIF_MM_INDACCESS_CNTL 0x1500
33 #define mmBIF_DOORBELL_APER_EN 0x1501
34 #define mmBUS_CNTL 0x1508
35 #define mmCONFIG_CNTL 0x1509
36 #define mmCONFIG_MEMSIZE 0x150a
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_catalog.c15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c26 /* Register Offset definitions for CMU_TOP (0x12060000) */
27 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
28 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
29 #define PLL_CON0_PLL_SHARED0 0x0100
30 #define PLL_CON0_PLL_SHARED1 0x0120
31 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
32 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
33 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
34 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
35 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
[all …]
H A Dclk-artpec8.c27 /* Register Offset definitions for CMU_CMU (0x12400000) */
28 #define PLL_LOCKTIME_PLL_AUDIO 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
30 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
31 #define PLL_CON0_PLL_AUDIO 0x0100
32 #define PLL_CON0_PLL_SHARED0 0x0120
33 #define PLL_CON0_PLL_SHARED1 0x0140
34 #define CLK_CON_MUX_CLKCMU_2D 0x1000
35 #define CLK_CON_MUX_CLKCMU_3D 0x1004
36 #define CLK_CON_MUX_CLKCMU_BUS 0x1008
[all …]

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