xref: /linux/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml (revision 2f2c7254931f41b5736e3ba12aaa9ac1bbeeeb92) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32MP25 PCIe Root Complex
8
9maintainers:
10  - Christian Bruel <christian.bruel@foss.st.com>
11
12description:
13  PCIe root complex controller based on the Synopsys DesignWare PCIe core.
14
15allOf:
16  - $ref: /schemas/pci/snps,dw-pcie.yaml#
17  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
18
19properties:
20  compatible:
21    const: st,stm32mp25-pcie-rc
22
23  reg:
24    items:
25      - description: Data Bus Interface (DBI) registers.
26      - description: PCIe configuration registers.
27
28  reg-names:
29    items:
30      - const: dbi
31      - const: config
32
33  msi-parent:
34    maxItems: 1
35
36patternProperties:
37  '^pcie@[0-2],0$':
38    type: object
39    $ref: /schemas/pci/pci-pci-bridge.yaml#
40
41    properties:
42      reg:
43        maxItems: 1
44
45      phys:
46        maxItems: 1
47
48      reset-gpios:
49        description: GPIO controlled connection to PERST# signal
50        maxItems: 1
51
52      wake-gpios:
53        description: GPIO used as WAKE# input signal
54        maxItems: 1
55
56    required:
57      - phys
58      - ranges
59
60    unevaluatedProperties: false
61
62required:
63  - interrupt-map
64  - interrupt-map-mask
65  - ranges
66  - dma-ranges
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
73    #include <dt-bindings/gpio/gpio.h>
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/phy/phy.h>
76    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
77
78    pcie@48400000 {
79        compatible = "st,stm32mp25-pcie-rc";
80        device_type = "pci";
81        reg = <0x48400000 0x400000>,
82              <0x10000000 0x10000>;
83        reg-names = "dbi", "config";
84        #interrupt-cells = <1>;
85        interrupt-map-mask = <0 0 0 7>;
86        interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
87                        <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
88                        <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
89                        <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
90        #address-cells = <3>;
91        #size-cells = <2>;
92        ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
93                 <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
94                 <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
95        dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
96        clocks = <&rcc CK_BUS_PCIE>;
97        resets = <&rcc PCIE_R>;
98        msi-parent = <&v2m0>;
99        access-controllers = <&rifsc 68>;
100        power-domains = <&CLUSTER_PD>;
101
102        pcie@0,0 {
103            device_type = "pci";
104            reg = <0x0 0x0 0x0 0x0 0x0>;
105            phys = <&combophy PHY_TYPE_PCIE>;
106            wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
107            reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
108            #address-cells = <3>;
109            #size-cells = <2>;
110            ranges;
111        };
112    };
113