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/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt6797.c18 * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
19 * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
24 PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
28 PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
32 PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
36 PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
55 .gpio_m = 0,
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8192-pinctrl.yaml149 reg = <0x10005000 0x1000>,
150 <0x11c20000 0x1000>,
151 <0x11d10000 0x1000>,
152 <0x11d30000 0x1000>,
153 <0x11d40000 0x1000>,
154 <0x11e20000 0x1000>,
155 <0x11e70000 0x1000>,
156 <0x11ea0000 0x1000>,
157 <0x11f20000 0x1000>,
158 <0x11f30000 0x1000>,
[all …]
H A Dmediatek,mt6893-pinctrl.yaml153 #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
159 reg = <0x10005000 0x1000>,
160 <0x11c20000 0x0200>,
161 <0x11d10000 0x0200>,
162 <0x11e20000 0x0200>,
163 <0x11e70000 0x0200>,
164 <0x11ea0000 0x0200>,
165 <0x11f20000 0x0200>,
166 <0x11f30000 0x0200>,
167 <0x1100b000 0x1000>;
[all …]
H A Dmediatek,mt6878-pinctrl.yaml165 #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
171 reg = <0x10005000 0x1000>,
172 <0x11d10000 0x1000>,
173 <0x11d30000 0x1000>,
174 <0x11d40000 0x1000>,
175 <0x11d50000 0x1000>,
176 <0x11d60000 0x1000>,
177 <0x11e20000 0x1000>,
178 <0x11e30000 0x1000>,
179 <0x11eb0000 0x1000>,
[all …]
H A Dmediatek,mt8189-pinctrl.yaml181 reg = <0x10005000 0x1000>,
182 <0x11b50000 0x1000>,
183 <0x11c50000 0x1000>,
184 <0x11c60000 0x1000>,
185 <0x11d20000 0x1000>,
186 <0x11d30000 0x1000>,
187 <0x11d40000 0x1000>,
188 <0x11e20000 0x1000>,
189 <0x11e30000 0x1000>,
190 <0x11f20000 0x1000>,
[all …]
H A Dmediatek,mt6779-pinctrl.yaml114 '-[0-9]*$':
158 enum: [0, 1]
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
170 enum: [0, 1, 2, 3]
177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
182 enum: [0, 1, 2, 3]
[all …]
H A Dmediatek,mt6795-pinctrl.yaml136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
141 enum: [0, 1, 2, 3]
148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
149 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
150 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
153 enum: [0, 1, 2, 3]
186 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
190 gpio-ranges = <&pio 0 0 196>;
H A Dmediatek,mt8188-pinctrl.yaml188 reg = <0x10005000 0x1000>,
189 <0x11c00000 0x1000>,
190 <0x11e10000 0x1000>,
191 <0x11e20000 0x1000>,
192 <0x11ea0000 0x1000>,
193 <0x1000b000 0x1000>;
199 gpio-ranges = <&pio 0 0 176>;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8186-pinctrl.yaml229 reg = <0x10005000 0x1000>,
230 <0x10002000 0x0200>,
231 <0x10002200 0x0200>,
232 <0x10002400 0x0200>,
233 <0x10002600 0x0200>,
234 <0x10002A00 0x0200>,
235 <0x10002c00 0x0200>,
236 <0x1000b000 0x1000>;
242 gpio-ranges = <&pio 0 0 185>;
244 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8195-pinctrl.yaml240 reg = <0x10005000 0x1000>,
241 <0x11d10000 0x1000>,
242 <0x11d30000 0x1000>,
243 <0x11d40000 0x1000>,
244 <0x11e20000 0x1000>,
245 <0x11eb0000 0x1000>,
246 <0x11f40000 0x1000>,
247 <0x1000b000 0x1000>;
253 gpio-ranges = <&pio 0 0 144>;
255 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
/linux/arch/arm/mach-versatile/
H A Dversatile.c25 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
33 #define VERSATILE_SYS_PCICTL_OFFSET 0x44
34 #define VERSATILE_SYS_MCI_OFFSET 0x48
39 #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
40 #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
41 #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
46 #define VERSATILE_REFCLK 0
87 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
166 versatile_sys_base = of_iomap(np, 0); in versatile_dt_init()
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
74 clock-frequency = <0>;
80 reg = <0x40000000 0x04000000>;
90 reg = <0x44000000 0x04000000>;
100 reg = <0x4e000000 0x10000>;
110 reg = <0x4f000000 0x20000>;
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 reg = <0x40000000 0x04000000>;
105 reg = <0x44000000 0x04000000>;
115 reg = <0x4e000000 0x10000>;
[all …]
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x38000000 0x800000>;
113 reg = <0x3c000000 0x4000000>;
121 reg = <0x3a000000 0x10000>;
[all …]
H A Darm-realview-pb11mp.dts45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8365.dtsi38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]

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