xref: /linux/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml (revision 186f3edfdd41f2ae87fc40a9ccba52a3bf930994) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek MT8189 Pin Controller
8
9maintainers:
10  - Lei Xue <lei.xue@mediatek.com>
11  - Cathy Xu <ot_cathy.xu@mediatek.com>
12
13description:
14  The MediaTek's MT8189 Pin controller is used to control SoC pins.
15
16properties:
17  compatible:
18    const: mediatek,mt8189-pinctrl
19
20  reg:
21    items:
22      - description: gpio base
23      - description: lm group IO
24      - description: rb0 group IO
25      - description: rb1 group IO
26      - description: bm0 group IO
27      - description: bm1 group IO
28      - description: bm2 group IO
29      - description: lt0 group IO
30      - description: lt1 group IO
31      - description: rt group IO
32      - description: eint0 group IO
33      - description: eint1 group IO
34      - description: eint2 group IO
35      - description: eint3 group IO
36      - description: eint4 group IO
37
38  reg-names:
39    items:
40      - const: base
41      - const: lm
42      - const: rb0
43      - const: rb1
44      - const: bm0
45      - const: bm1
46      - const: bm2
47      - const: lt0
48      - const: lt1
49      - const: rt
50      - const: eint0
51      - const: eint1
52      - const: eint2
53      - const: eint3
54      - const: eint4
55
56  interrupts:
57    maxItems: 1
58
59  interrupt-controller: true
60
61  '#interrupt-cells':
62    const: 2
63
64  gpio-controller: true
65
66  '#gpio-cells':
67    const: 2
68
69  gpio-ranges:
70    maxItems: 1
71
72  gpio-line-names: true
73
74# PIN CONFIGURATION NODES
75patternProperties:
76  '-pins$':
77    type: object
78    additionalProperties: false
79
80    patternProperties:
81      '^pins':
82        type: object
83        $ref: /schemas/pinctrl/pincfg-node.yaml
84        additionalProperties: false
85        description:
86          A pinctrl node should contain at least one subnode representing the
87          pinctrl groups available on the machine. Each subnode will list the
88          pins it needs, and how they should be configured, with regard to muxer
89          configuration, pullups, drive strength, input enable/disable and input
90          schmitt.
91
92        properties:
93          pinmux:
94            description:
95              Integer array, represents gpio pin number and mux setting.
96              Supported pin number and mux varies for different SoCs, and are
97              defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
98              directly, for this SoC.
99
100          drive-strength:
101            enum: [2, 4, 6, 8, 10, 12, 14, 16]
102
103          bias-pull-down:
104            oneOf:
105              - type: boolean
106              - enum: [100, 101, 102, 103]
107                description: mt8189 pull down PUPD/R0/R1 type define value.
108              - enum: [75000, 5000]
109                description: mt8189 pull down RSEL type si unit value(ohm).
110            description: |
111              For pull down type is normal, it doesn't need add R1R0 define
112              and resistance value.
113
114              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
115              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
116              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
117              "MTK_PUPD_SET_R1R0_11" define in mt8189.
118
119              For pull down type is PD/RSEL, it can add resistance value(ohm)
120              to set different resistance by identifying property
121              "mediatek,rsel-resistance-in-si-unit".
122
123          bias-pull-up:
124            oneOf:
125              - type: boolean
126              - enum: [100, 101, 102, 103]
127                description: mt8189 pull up PUPD/R0/R1 type define value.
128              - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
129                description: mt8189 pull up RSEL type si unit value(ohm).
130            description: |
131              For pull up type is normal, it don't need add R1R0 define
132              and resistance value.
133
134              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
135              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
136              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
137              "MTK_PUPD_SET_R1R0_11" define in mt8189.
138
139              For pull up type is PU/RSEL, it can add resistance value(ohm)
140              to set different resistance by identifying property
141              "mediatek,rsel-resistance-in-si-unit".
142
143          bias-disable: true
144
145          output-high: true
146
147          output-low: true
148
149          input-enable: true
150
151          input-disable: true
152
153          input-schmitt-enable: true
154
155          input-schmitt-disable: true
156
157        required:
158          - pinmux
159
160required:
161  - compatible
162  - reg
163  - interrupts
164  - interrupt-controller
165  - '#interrupt-cells'
166  - gpio-controller
167  - '#gpio-cells'
168  - gpio-ranges
169
170additionalProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/pinctrl/mt65xx.h>
175    #include <dt-bindings/interrupt-controller/arm-gic.h>
176    #define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
177    #define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
178
179    pio: pinctrl@10005000 {
180        compatible = "mediatek,mt8189-pinctrl";
181        reg = <0x10005000 0x1000>,
182              <0x11b50000 0x1000>,
183              <0x11c50000 0x1000>,
184              <0x11c60000 0x1000>,
185              <0x11d20000 0x1000>,
186              <0x11d30000 0x1000>,
187              <0x11d40000 0x1000>,
188              <0x11e20000 0x1000>,
189              <0x11e30000 0x1000>,
190              <0x11f20000 0x1000>,
191              <0x11ce0000 0x1000>,
192              <0x11de0000 0x1000>,
193              <0x11e60000 0x1000>,
194              <0x1c01e000 0x1000>,
195              <0x11f00000 0x1000>;
196        reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1",
197                    "bm2", "lt0", "lt1", "rt", "eint0", "eint1",
198                    "eint2", "eint3", "eint4";
199        gpio-controller;
200        #gpio-cells = <2>;
201        gpio-ranges = <&pio 0 0 182>;
202        interrupt-controller;
203        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
204        #interrupt-cells = <2>;
205
206        i2c0-pins {
207            pins {
208                pinmux = <PINMUX_GPIO51__FUNC_SCL0>,
209                         <PINMUX_GPIO52__FUNC_SDA0>;
210                bias-disable;
211            };
212        };
213    };
214