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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
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/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h24 #define AR_BT_COEX_MODE 0x8170
25 #define AR_BT_TIME_EXTEND 0x000000ff
26 #define AR_BT_TIME_EXTEND_S 0
27 #define AR_BT_TXSTATE_EXTEND 0x00000100
29 #define AR_BT_TX_FRAME_EXTEND 0x00000200
31 #define AR_BT_MODE 0x00000c00
33 #define AR_BT_QUIET 0x00001000
35 #define AR_BT_QCU_THRESH 0x0001e000
37 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
39 #define AR_BT_PRIORITY_TIME 0x00fc0000
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.txt321 reg = <0x1b500000 0x1000
322 0x1b502000 0x80
323 0x1b600000 0x100
324 0x0ff00000 0x100000>;
327 linux,pci-domain = <0>;
328 bus-range = <0x00 0xff>;
332 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
333 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
337 interrupt-map-mask = <0 0 0 0x7>;
338 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
[all …]
H A Dqcom,pcie.yaml588 reg = <0x1b500000 0x1000>,
589 <0x1b502000 0x80>,
590 <0x1b600000 0x100>,
591 <0x0ff00000 0x100000>;
594 linux,pci-domain = <0>;
595 bus-range = <0x00 0xff>;
599 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
600 <0x82000000 0 0 0x08000000 0 0x07e00000>;
604 interrupt-map-mask = <0 0 0 0x7>;
605 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drx.h14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x
[all...]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV()
47 ::memset(&reg_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV()
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0; in CountITSize()
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/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]