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/linux/drivers/media/pci/cx18/
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/linux/drivers/ufs/host/
H A Dufs-renesas.c26 SET_PHY_INDEX_LO = 0,
58 PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
61 PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
62 PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
63 PARAM_WRITE(0xd0, 0x0000080c), \
64 PARAM_POLL(0xd4, BIT(8), BIT(8))
67 PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
68 PARAM_WRITE(0xd0, 0x00000800), \
69 PARAM_RESTORE(0xd4, _index), \
70 PARAM_WRITE(0xd0, 0x0000080c), \
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dtable.c7 0x01c, 0x07000000,
8 0x800, 0x00040000,
9 0x804, 0x00008003,
10 0x808, 0x0000fc00,
11 0x80c, 0x0000000a,
12 0x810, 0x10005088,
13 0x814, 0x020c3d10,
14 0x818, 0x00200185,
15 0x81c, 0x00000000,
16 0x820, 0x01000000,
[all …]
/linux/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml40 BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
63 reg = <0x0 0x40000000 0x0 0x1000000>;
64 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
70 iommu-map = <0x0 &iommu0 0x0 0x8
71 0x9 &iommu0 0x9 0xfff7>;
74 iommu0: iommu@1,0 {
76 reg = <0x800 0 0 0 0>;
85 reg = <0x0 0x50000000 0x0 0x1000000>;
86 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
90 * with endpoint IDs 0x10000 - 0x1ffff
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/linux/sound/soc/fsl/
H A Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]
/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
48 cond1 &= 0x000F0FFF; in CheckPositive()
49 driver1 &= 0x000F0FFF; in CheckPositive()
52 u32 bitMask = 0; in CheckPositive()
53 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive()
56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
57 bitMask |= 0x000000FF; in CheckPositive()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-atl-x530.dts24 reg = <0x00000000 0x40000000>; /* 1GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
35 pinctrl-0 = <&i2c0_pins>;
41 pinctrl-0 = <&uart0_pins>;
49 segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>,
79 devbus,badr-skew-ps = <0>;
82 devbus,rd-setup-ps = <0>;
83 devbus,rd-hold-ps = <0>;
[all …]
/linux/drivers/bus/
H A Dda8xx-mstpri.c29 #define DA8XX_MSTPRI0_OFFSET 0
34 DA8XX_MSTPRI_ARM_I = 0,
62 .shift = 0,
63 .mask = 0x0000000f,
68 .mask = 0x000000f0,
73 .mask = 0x000f0000,
78 .mask = 0x00f00000,
82 .shift = 0,
83 .mask = 0x0000000f,
88 .mask = 0x000000f0,
[all …]
/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_err.h16 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
17 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
18 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
22 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
24 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
25 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
26 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
27 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
28 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
29 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg94.c39 nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark); in g94_sor_dp_watermark()
49 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2); in g94_sor_dp_activesym()
50 nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8); in g94_sor_dp_activesym()
59 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym()
60 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym()
71 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
72 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
73 data[2] = nvkm_rd32(device, 0x61c130 + loff); in g94_sor_dp_drive()
74 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive()
75 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive()
[all …]
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c45 #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
66 if (ring->me == 0) in vce_v4_0_ring_get_rptr()
67 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
69 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
71 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
88 if (ring->me == 0) in vce_v4_0_ring_get_wptr()
89 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
91 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
93 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
114 if (ring->me == 0) in vce_v4_0_ring_set_wptr()
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Ddcb.c32 u16 dcb = 0x0000; in dcb_table()
35 dcb = nvbios_rd16(bios, 0x36); in dcb_table()
43 if (*ver >= 0x42) { in dcb_table()
44 nvkm_warn(subdev, "DCB version 0x%02x unknown\n", *ver); in dcb_table()
45 return 0x0000; in dcb_table()
47 if (*ver >= 0x30) { in dcb_table()
48 if (nvbios_rd32(bios, dcb + 6) == 0x4edcbdcb) { in dcb_table()
55 if (*ver >= 0x20) { in dcb_table()
56 if (nvbios_rd32(bios, dcb + 4) == 0x4edcbdcb) { in dcb_table()
64 if (*ver >= 0x15) { in dcb_table()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_debug.h11 I40E_DEBUG_INIT = 0x00000001,
12 I40E_DEBUG_RELEASE = 0x00000002,
14 I40E_DEBUG_LINK = 0x00000010,
15 I40E_DEBUG_PHY = 0x00000020,
16 I40E_DEBUG_HMC = 0x00000040,
17 I40E_DEBUG_NVM = 0x00000080,
18 I40E_DEBUG_LAN = 0x00000100,
19 I40E_DEBUG_FLOW = 0x00000200,
20 I40E_DEBUG_DCB = 0x00000400,
21 I40E_DEBUG_DIAG = 0x00000800,
[all …]
/linux/arch/sh/configs/
H A Dsh7757lcr_defconfig16 CONFIG_MEMORY_START=0x40000000
17 CONFIG_MEMORY_SIZE=0x0f000000
/linux/arch/powerpc/include/asm/nohash/
H A Dmmu-e500.h9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
[all …]
/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c10 #define LATTER_STF 0xffff00000004ULL
11 #define LATTER_ISOC_CHANNELS 0xffff00000008ULL
12 #define LATTER_ISOC_START 0xffff0000000cULL
13 #define LATTER_FETCH_MODE 0xffff00000010ULL
14 #define LATTER_SYNC_STATUS 0x0000801c0000ULL
19 // 0xf0000000: (unidentified)
20 // 0x0f000000: effective rate of sampling clock
21 // 0x00f00000: detected rate of word clock on BNC interface
22 // 0x000f0000: detected rate of ADAT or S/PDIF on optical interface
23 // 0x0000f000: detected rate of S/PDIF on coaxial interface
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Dpsrcompat.h8 #define PSR_CWP 0x0000001f /* current window pointer */
9 #define PSR_ET 0x00000020 /* enable traps field */
10 #define PSR_PS 0x00000040 /* previous privilege level */
11 #define PSR_S 0x00000080 /* current privilege level */
12 #define PSR_PIL 0x00000f00 /* processor interrupt level */
13 #define PSR_EF 0x00001000 /* enable floating point */
14 #define PSR_EC 0x00002000 /* enable co-processor */
15 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */
16 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */
17 #define PSR_ICC 0x00f00000 /* integer condition codes */
[all …]

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