Lines Matching +full:0 +full:x0f000000
24 reg = <0x00000000 0x40000000>; /* 1GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
35 pinctrl-0 = <&i2c0_pins>;
41 pinctrl-0 = <&uart0_pins>;
49 segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>,
79 devbus,badr-skew-ps = <0>;
82 devbus,rd-setup-ps = <0>;
83 devbus,rd-hold-ps = <0>;
86 devbus,sync-enable = <0>;
91 nvs@0 {
95 reg = <0 0x00080000>;
102 i2c0_gpio_pins: i2c-gpio-pins-0 {
113 pinctrl-0 = <&i2c0_pins>;
120 #size-cells = <0>;
122 reg = <0x71>;
125 i2c@0 { /* POE devices MUX */
127 #size-cells = <0>;
128 reg = <0>;
133 #size-cells = <0>;
138 reg = <0x2e>;
143 reg = <0x2d>;
149 #size-cells = <0>;
154 reg = <0x68>;
160 #size-cells = <0>;
167 reg = <0x20>;
179 pinctrl-0 = <&spi1_pins>;
193 partition@0 {
194 reg = <0x00000000 0x00100000>;
198 reg = <0x00100000 0x00040000>;
202 reg = <0x00140000 0x00e80000>;
206 reg = <0x00fc0000 0x00040000>;
216 nand@0 {
217 reg = <0>;
218 label = "pxa3xx_nand-0";
219 nand-rb = <0>;
230 partition@0 {
231 reg = <0x00000000 0x0f000000>;
236 reg = <0x0f000000 0x00800000>;
240 reg = <0x0f800000 0x00800000>;