Home
last modified time | relevance | path

Searched +full:0 +full:x0e700000 (Results 1 – 16 of 16) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dqcom,spmi-pmic.yaml30 - pattern: '^pm(a|s)?[0-9]*@.*$'
108 const: 0
123 "^adc@[0-9a-f]+$":
130 "^adc-tm@[0-9a-f]+$":
134 "^audio-codec@[0-9a-f]+$":
138 "^battery@[0-9a-f]+$":
143 "^charger@[0-9a-f]+$":
151 "gpio@[0-9a-f]+$":
155 "^led-controller@[0-9a-f]+$":
159 "^nvram@[0
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi52 #clock-cells = <0>;
58 pinctrl-0 = <&divclk4_pin_a>;
98 pinctrl-0 = <&hall_front_default &hall_back_default>;
129 reg = <0 0x00200000 0 0x100000>;
134 reg = <0 0x00300000 0
[all...]
H A Dsdm670.dtsi33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x20
[all...]
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x10
[all...]
H A Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dsc8180x.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
58 clocks = <&cpufreq_hw 0>;
76 reg = <0x0 0x10
[all...]
H A Dsm8350.dtsi37 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
57 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x10
[all...]
H A Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x10
[all...]
H A Dsm8150.dtsi32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x10
[all...]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x10
[all...]
H A Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsc7280.dtsi80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x60000
[all...]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
[all...]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]