Lines Matching +full:0 +full:x0e700000
25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
91 reg = <0x0 0x300>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
106 reg = <0x0 0x10000>;
127 reg = <0x0 0x10100>;
142 reg = <0x0 0x10200>;
157 reg = <0x0 0x10300>;
301 reg = <0x0 0x80000000 0x0 0x0>;
329 reg = <0x0 0x80000000 0x0 0x10000000>;
334 reg = <0x0 0x90000000 0x0 0x600000>;
339 reg = <0x0 0x90600000 0x0 0x200000>;
344 reg = <0x0 0x90800000 0x0 0x60000>;
350 reg = <0x0 0x90860000 0x0 0x20000>;
355 reg = <0x0 0x908b0000 0x0 0x10000>;
360 reg = <0x0 0x908f0000 0x0 0xf000>;
365 reg = <0x0 0x908ff000 0x0 0x1000>;
371 reg = <0x0 0x90900000 0x0 0x200000>;
377 reg = <0x0 0x90b00000 0x0 0x100000>;
382 reg = <0x0 0x93b00000 0x0 0xf00000>;
387 reg = <0x0 0x94a00000 0x0 0x800000>;
392 reg = <0x0 0x95200000 0x0 0x500000>;
397 reg = <0x0 0x95c00000 0x0 0x1e00000>;
402 reg = <0x0 0x97b00000 0x0 0x1e00000>;
407 reg = <0x0 0x99900000 0x0 0x1e00000>;
412 reg = <0x0 0x9b800000 0x0 0x1e00000>;
417 reg = <0x0 0x9d600000 0x0 0x2000>;
422 reg = <0x0 0x9d700000 0x0 0x1e00000>;
427 reg = <0x0 0x9f500000 0x0 0x700000>;
432 reg = <0x0 0x9fc00000 0x0 0x700000>;
437 reg = <0x0 0xbeb00000 0x0 0x11500000>;
442 reg = <0x0 0xd0000000 0x0 0x100000>;
447 reg = <0x0 0xd0100000 0x0 0x1200000>;
452 reg = <0x0 0xd1300000 0x0 0x500000>;
457 reg = <0x0 0xd1800000 0x0 0x3900000>;
462 soc: soc@0 {
466 ranges = <0 0 0 0 0x10 0>;
470 reg = <0x0 0x00100000 0x0 0xc7018>;
476 <0>,
477 <0>,
478 <0>,
481 <0>,
482 <0>,
483 <0>,
486 <0>,
487 <0>,
488 <0>;
494 reg = <0x0 0x00408000 0x0 0x1000>;
503 reg = <0x0 0x008c0000 0x0 0x6000>;
508 iommus = <&apps_smmu 0x5a3 0x0>;
515 reg = <0x0 0x880000 0x0 0x4000>;
517 #size-cells = <0>;
536 reg = <0x0 0x880000 0x0 0x4000>;
538 #size-cells = <0>;
557 reg = <0x0 0x884000 0x0 0x4000>;
559 #size-cells = <0>;
578 reg = <0x0 0x884000 0x0 0x4000>;
580 #size-cells = <0>;
599 reg = <0x0 0x888000 0x0 0x4000>;
601 #size-cells = <0>;
620 reg = <0x0 0x00888000 0x0 0x4000>;
635 #size-cells = <0>;
641 reg = <0x0 0x88c000 0x0 0x4000>;
643 #size-cells = <0>;
662 reg = <0x0 0x88c000 0x0 0x4000>;
664 #size-cells = <0>;
683 reg = <0x0 0x0088c000 0x0 0x4000>;
698 reg = <0x0 0x00890000 0x0 0x4000>;
713 #size-cells = <0>;
719 reg = <0x0 0x890000 0x0 0x4000>;
721 #size-cells = <0>;
740 reg = <0x0 0x894000 0x0 0x4000>;
742 #size-cells = <0>;
761 reg = <0x0 0x894000 0x0 0x4000>;
763 #size-cells = <0>;
782 reg = <0x0 0x898000 0x0 0x4000>;
784 #size-cells = <0>;
803 reg = <0x0 0x898000 0x0 0x4000>;
805 #size-cells = <0>;
825 reg = <0x0 0x9c0000 0x0 0x6000>;
832 iommus = <&apps_smmu 0x403 0x0>;
837 reg = <0x0 0x980000 0x0 0x4000>;
839 #size-cells = <0>;
858 reg = <0x0 0x980000 0x0 0x4000>;
860 #size-cells = <0>;
879 reg = <0x0 0x984000 0x0 0x4000>;
881 #size-cells = <0>;
900 reg = <0x0 0x984000 0x0 0x4000>;
902 #size-cells = <0>;
921 reg = <0x0 0x988000 0x0 0x4000>;
923 #size-cells = <0>;
942 reg = <0x0 0x988000 0x0 0x4000>;
944 #size-cells = <0>;
963 reg = <0x0 0x98c000 0x0 0x4000>;
965 #size-cells = <0>;
984 reg = <0x0 0x98c000 0x0 0x4000>;
986 #size-cells = <0>;
1005 reg = <0x0 0x990000 0x0 0x4000>;
1007 #size-cells = <0>;
1026 reg = <0x0 0x990000 0x0 0x4000>;
1028 #size-cells = <0>;
1047 reg = <0x0 0x994000 0x0 0x4000>;
1049 #size-cells = <0>;
1068 reg = <0x0 0x994000 0x0 0x4000>;
1070 #size-cells = <0>;
1089 reg = <0x0 0x994000 0x0 0x4000>;
1105 reg = <0x0 0x00ac0000 0x0 0x6000>;
1112 iommus = <&apps_smmu 0x443 0x0>;
1117 reg = <0x0 0xa80000 0x0 0x4000>;
1119 #size-cells = <0>;
1138 reg = <0x0 0xa80000 0x0 0x4000>;
1140 #size-cells = <0>;
1159 reg = <0x0 0xa84000 0x0 0x4000>;
1161 #size-cells = <0>;
1180 reg = <0x0 0xa84000 0x0 0x4000>;
1182 #size-cells = <0>;
1201 reg = <0x0 0xa88000 0x0 0x4000>;
1203 #size-cells = <0>;
1222 reg = <0x0 0xa88000 0x0 0x4000>;
1224 #size-cells = <0>;
1243 reg = <0x0 0xa88000 0x0 0x4000>;
1258 reg = <0x0 0xa8c000 0x0 0x4000>;
1260 #size-cells = <0>;
1279 reg = <0x0 0xa8c000 0x0 0x4000>;
1281 #size-cells = <0>;
1300 reg = <0x0 0x00a8c000 0x0 0x4000>;
1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1306 &clk_virt SLAVE_QUP_CORE_1 0>,
1307 <&gem_noc MASTER_APPSS_PROC 0
1308 &config_noc SLAVE_QUP_1 0>;
1316 reg = <0x0 0xa90000 0x0 0x4000>;
1318 #size-cells = <0>;
1337 reg = <0x0 0xa90000 0x0 0x4000>;
1339 #size-cells = <0>;
1358 reg = <0x0 0xa94000 0x0 0x4000>;
1360 #size-cells = <0>;
1379 reg = <0x0 0xa94000 0x0 0x4000>;
1381 #size-cells = <0>;
1400 reg = <0x0 0x00a94000 0x0 0x4000>;
1415 reg = <0x0 0xa98000 0x0 0x4000>;
1417 #size-cells = <0>;
1437 reg = <0x0 0xbc0000 0x0 0x6000>;
1444 iommus = <&apps_smmu 0x43 0x0>;
1449 reg = <0x0 0xb80000 0x0 0x4000>;
1451 #size-cells = <0>;
1470 reg = <0x0 0xb80000 0x0 0x4000>;
1472 #size-cells = <0>;
1492 reg = <0 0x010d2000 0 0x1000>;
1497 reg = <0x0 0x01d84000 0x0 0x3000>;
1507 iommus = <&apps_smmu 0x100 0x0>;
1526 <0 0>,
1527 <0 0>,
1529 <0 0>,
1530 <0 0>,
1531 <0 0>,
1532 <0 0>;
1539 reg = <0x0 0x01d87000 0x0 0xe10>;
1549 resets = <&ufs_mem_hc 0>;
1551 #phy-cells = <0>;
1558 reg = <0x0 0x01d88000 0x0 0x8000>;
1565 reg = <0 0x088e4000 0 0x120>;
1570 #phy-cells = <0>;
1577 reg = <0 0x088e8000 0 0x2000>;
1591 #clock-cells = <0>;
1594 #phy-cells = <0>;
1601 reg = <0 0x0a6f8800 0 0x400>;
1631 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1641 reg = <0 0x0a600000 0 0xe000>;
1643 iommus = <&apps_smmu 0x080 0x0>;
1652 reg = <0 0x088e6000 0 0x120>;
1657 #phy-cells = <0>;
1664 reg = <0 0x088ea000 0 0x2000>;
1678 #clock-cells = <0>;
1681 #phy-cells = <0>;
1688 reg = <0 0x0a8f8800 0 0x400>;
1718 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1728 reg = <0 0x0a800000 0 0xe000>;
1730 iommus = <&apps_smmu 0x0a0 0x0>;
1739 reg = <0 0x088e7000 0 0x120>;
1744 #phy-cells = <0>;
1751 reg = <0 0x0a4f8800 0 0x400>;
1779 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
1780 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
1789 reg = <0 0x0a400000 0 0xe000>;
1791 iommus = <&apps_smmu 0x020 0x0>;
1799 reg = <0x0 0x01f40000 0x0 0x20000>;
1805 reg = <0x0 0x03d90000 0x0 0xa000>;
1820 reg = <0x0 0x03da0000 0x0 0x20000>;
1855 reg = <0x0 0x08901000 0x0 0xe10>;
1858 #phy-cells = <0>;
1864 reg = <0x0 0x08902000 0x0 0xe10>;
1867 #phy-cells = <0>;
1873 reg = <0x0 0x0b220000 0x0 0x30000>,
1874 <0x0 0x17c000f0 0x0 0x64>;
1875 qcom,pdc-ranges = <0 480 40>,
1920 reg = <0x0 0x0c251000 0x0 0x1ff>,
1921 <0x0 0x0c224000 0x0 0x8>;
1931 reg = <0x0 0x0c252000 0x0 0x1ff>,
1932 <0x0 0x0c225000 0x0 0x8>;
1942 reg = <0x0 0x0c263000 0x0 0x1ff>,
1943 <0x0 0x0c222000 0x0 0x8>;
1953 reg = <0x0 0x0c265000 0x0 0x1ff>,
1954 <0x0 0x0c223000 0x0 0x8>;
1964 reg = <0x0 0x0c300000 0x0 0x400>;
1969 #clock-cells = <0>;
1974 reg = <0x0 0x0c3f0000 0x0 0x400>;
1979 reg = <0x0 0x0c440000 0x0 0x1100>,
1980 <0x0 0x0c600000 0x0 0x2000000>,
1981 <0x0 0x0e600000 0x0 0x100000>,
1982 <0x0 0x0e700000 0x0 0xa0000>,
1983 <0x0 0x0c40a000 0x0 0x26000>;
1989 qcom,channel = <0>;
1990 qcom,ee = <0>;
1996 #size-cells = <0>;
2001 reg = <0x0 0x0f000000 0x0 0x1000000>;
2007 gpio-ranges = <&tlmm 0 0 149>;
2013 reg = <0x0 0x15000000 0x0 0x100000>;
2151 reg = <0x0 0x15200000 0x0 0x80000>;
2225 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2226 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2231 redistributor-stride = <0x0 0x20000>;
2236 reg = <0x0 0x17c10000 0x0 0x1000>;
2238 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
2243 reg = <0x0 0x17c20000 0x0 0x1000>;
2244 ranges = <0x0 0x0 0x0 0x20000000>;
2249 reg = <0x17c21000 0x1000>,
2250 <0x17c22000 0x1000>;
2253 frame-number = <0>;
2257 reg = <0x17c23000 0x1000>;
2264 reg = <0x17c25000 0x1000>;
2271 reg = <0x17c27000 0x1000>;
2278 reg = <0x17c29000 0x1000>;
2285 reg = <0x17c2b000 0x1000>;
2292 reg = <0x17c2d000 0x1000>;
2301 reg = <0x0 0x18200000 0x0 0x10000>,
2302 <0x0 0x18210000 0x0 0x10000>,
2303 <0x0 0x18220000 0x0 0x10000>;
2304 reg-names = "drv-0", "drv-1", "drv-2";
2308 qcom,tcs-offset = <0xd00>;
2313 <CONTROL_TCS 0>;
2335 rpmhpd_opp_ret: opp-0 {
2381 reg = <0x0 0x18591000 0x0 0x1000>,
2382 <0x0 0x18593000 0x0 0x1000>;
2393 reg = <0x0 0x23000000 0x0 0x10000>,
2394 <0x0 0x23016000 0x0 0x100>;
2414 iommus = <&apps_smmu 0x140 0xf>;
2426 reg = <0x0 0x23040000 0x0 0x10000>,
2427 <0x0 0x23056000 0x0 0x100>;
2447 iommus = <&apps_smmu 0x120 0xf>;
2459 aoss-0-thermal {
2460 polling-delay-passive = <0>;
2461 polling-delay = <0>;
2463 thermal-sensors = <&tsens0 0>;
2480 cpu-0-0-0-thermal {
2482 polling-delay = <0>;
2501 cpu-0-1-0-thermal {
2503 polling-delay = <0>;
2522 cpu-0-2-0-thermal {
2524 polling-delay = <0>;
2543 cpu-0-3-0-thermal {
2545 polling-delay = <0>;
2564 gpuss-0-thermal {
2566 polling-delay = <0>;
2587 polling-delay = <0>;
2608 polling-delay = <0>;
2628 polling-delay-passive = <0>;
2629 polling-delay = <0>;
2648 camss-0-thermal {
2649 polling-delay-passive = <0>;
2650 polling-delay = <0>;
2669 pcie-0-thermal {
2670 polling-delay-passive = <0>;
2671 polling-delay = <0>;
2690 cpuss-0-0-thermal {
2691 polling-delay-passive = <0>;
2692 polling-delay = <0>;
2712 polling-delay-passive = <0>;
2713 polling-delay = <0>;
2715 thermal-sensors = <&tsens1 0>;
2732 cpu-0-0-1-thermal {
2734 polling-delay = <0>;
2753 cpu-0-1-1-thermal {
2755 polling-delay = <0>;
2774 cpu-0-2-1-thermal {
2776 polling-delay = <0>;
2795 cpu-0-3-1-thermal {
2797 polling-delay = <0>;
2818 polling-delay = <0>;
2839 polling-delay = <0>;
2860 polling-delay = <0>;
2880 polling-delay-passive = <0>;
2881 polling-delay = <0>;
2901 polling-delay-passive = <0>;
2902 polling-delay = <0>;
2922 polling-delay-passive = <0>;
2923 polling-delay = <0>;
2942 cpuss-0-1-thermal {
2943 polling-delay-passive = <0>;
2944 polling-delay = <0>;
2964 polling-delay-passive = <0>;
2965 polling-delay = <0>;
2967 thermal-sensors = <&tsens2 0>;
2984 cpu-1-0-0-thermal {
2986 polling-delay = <0>;
3005 cpu-1-1-0-thermal {
3007 polling-delay = <0>;
3026 cpu-1-2-0-thermal {
3028 polling-delay = <0>;
3047 cpu-1-3-0-thermal {
3049 polling-delay = <0>;
3068 nsp-0-0-0-thermal {
3070 polling-delay = <0>;
3089 nsp-0-1-0-thermal {
3091 polling-delay = <0>;
3110 nsp-0-2-0-thermal {
3112 polling-delay = <0>;
3131 nsp-1-0-0-thermal {
3133 polling-delay = <0>;
3152 nsp-1-1-0-thermal {
3154 polling-delay = <0>;
3173 nsp-1-2-0-thermal {
3175 polling-delay = <0>;
3194 ddrss-0-thermal {
3195 polling-delay-passive = <0>;
3196 polling-delay = <0>;
3215 cpuss-1-0-thermal {
3216 polling-delay-passive = <0>;
3217 polling-delay = <0>;
3237 polling-delay-passive = <0>;
3238 polling-delay = <0>;
3240 thermal-sensors = <&tsens3 0>;
3257 cpu-1-0-1-thermal {
3259 polling-delay = <0>;
3280 polling-delay = <0>;
3301 polling-delay = <0>;
3322 polling-delay = <0>;
3341 nsp-0-0-1-thermal {
3343 polling-delay = <0>;
3362 nsp-0-1-1-thermal {
3364 polling-delay = <0>;
3383 nsp-0-2-1-thermal {
3385 polling-delay = <0>;
3404 nsp-1-0-1-thermal {
3406 polling-delay = <0>;
3427 polling-delay = <0>;
3448 polling-delay = <0>;
3468 polling-delay-passive = <0>;
3469 polling-delay = <0>;
3489 polling-delay-passive = <0>;
3490 polling-delay = <0>;
3520 reg = <0x0 0x01c00000 0x0 0x3000>,
3521 <0x0 0x40000000 0x0 0xf20>,
3522 <0x0 0x40000f20 0x0 0xa8>,
3523 <0x0 0x40001000 0x0 0x4000>,
3524 <0x0 0x40100000 0x0 0x100000>,
3525 <0x0 0x01c03000 0x0 0x1000>;
3531 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
3532 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
3533 bus-range = <0x00 0xff>;
3537 linux,pci-domain = <0>;
3551 interrupt-map-mask = <0 0 0 0x7>;
3552 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
3553 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
3554 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
3555 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
3572 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
3573 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
3576 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
3577 <0x100 &pcie_smmu 0x0001 0x1>;
3591 reg = <0x0 0x1c04000 0x0 0x2000>;
3610 #clock-cells = <0>;
3613 #phy-cells = <0>;
3620 reg = <0x0 0x01c10000 0x0 0x3000>,
3621 <0x0 0x60000000 0x0 0xf20>,
3622 <0x0 0x60000f20 0x0 0xa8>,
3623 <0x0 0x60001000 0x0 0x4000>,
3624 <0x0 0x60100000 0x0 0x100000>,
3625 <0x0 0x01c13000 0x0 0x1000>;
3631 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
3632 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
3633 bus-range = <0x00 0xff>;
3651 interrupt-map-mask = <0 0 0 0x7>;
3652 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
3653 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
3654 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
3655 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
3672 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
3673 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
3676 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
3677 <0x100 &pcie_smmu 0x0081 0x1>;
3691 reg = <0x0 0x1c14000 0x0 0x4000>;
3710 #clock-cells = <0>;
3713 #phy-cells = <0>;