Lines Matching +full:0 +full:x0e700000
37 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
57 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0x0 0x200>;
100 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0x0 0x300>;
119 clocks = <&cpufreq_hw 0>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
137 reg = <0x0 0x400>;
156 reg = <0x0 0x500>;
175 reg = <0x0 0x600>;
194 reg = <0x0 0x700>;
249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
252 arm,psci-suspend-param = <0x40000004>;
259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
262 arm,psci-suspend-param = <0x40000004>;
271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
273 arm,psci-suspend-param = <0x41000044>;
281 arm,psci-suspend-param = <0x4100c344>;
292 qcom,dload-mode = <&tcsr 0x13000>;
300 reg = <0x0 0x80000000 0x0 0x0>;
313 #power-domain-cells = <0>;
319 #power-domain-cells = <0>;
325 #power-domain-cells = <0>;
331 #power-domain-cells = <0>;
337 #power-domain-cells = <0>;
343 #power-domain-cells = <0>;
349 #power-domain-cells = <0>;
355 #power-domain-cells = <0>;
361 #power-domain-cells = <0>;
410 reg = <0x0 0x80000000 0x0 0x600000>;
416 reg = <0x0 0x80700000 0x0 0x160000>;
421 reg = <0x0 0x80860000 0x0 0x20000>;
426 reg = <0x0 0x80880000 0x0 0x14000>;
432 reg = <0x0 0x80900000 0x0 0x200000>;
438 reg = <0x0 0x80b00000 0x0 0x100000>;
443 reg = <0x0 0x80c00000 0x0 0x4600000>;
448 reg = <0x0 0x85200000 0x0 0x500000>;
453 reg = <0x0 0x85700000 0x0 0x500000>;
458 reg = <0x0 0x85c00000 0x0 0x500000>;
463 reg = <0x0 0x86100000 0x0 0x2100000>;
468 reg = <0x0 0x88200000 0x0 0x1500000>;
473 reg = <0x0 0x89700000 0x0 0x1e00000>;
478 reg = <0x0 0x8b500000 0x0 0x10000>;
483 reg = <0x0 0x8b510000 0x0 0xa000>;
488 reg = <0x0 0x8b51a000 0x0 0x2000>;
493 reg = <0x0 0x8b600000 0x0 0x100000>;
498 reg = <0x0 0x8b800000 0x0 0x10000000>;
504 reg = <0x0 0x9b800000 0x0 0x280000>;
512 reg = <0x0 0xd0000000 0x0 0x800000>;
517 reg = <0x0 0xd0800000 0x0 0x76f7000>;
522 reg = <0x0 0xd7ef7000 0x0 0x9000>;
527 reg = <0x0 0xd7f00000 0x0 0x80000>;
532 reg = <0x0 0xd7f80000 0x0 0x80000>;
537 reg = <0x0 0xd8800000 0x0 0x6800000>;
551 qcom,local-pid = <0>;
575 qcom,local-pid = <0>;
599 qcom,local-pid = <0>;
634 qcom,local-pid = <0>;
649 soc: soc@0 {
652 ranges = <0 0 0 0 0x10 0>;
653 dma-ranges = <0 0 0 0 0x10 0>;
658 reg = <0x0 0x00100000 0x0 0x1f0000>;
678 <0>,
679 <0>,
680 <0>,
681 <&ufs_mem_phy 0>,
685 <0>;
690 reg = <0 0x00408000 0 0x1000>;
699 reg = <0 0x00800000 0 0x60000>;
713 dma-channel-mask = <0xff>;
714 iommus = <&apps_smmu 0x5f6 0x0>;
721 reg = <0x0 0x008c0000 0x0 0x6000>;
725 iommus = <&apps_smmu 0x5e3 0x0>;
733 reg = <0 0x00880000 0 0x4000>;
737 pinctrl-0 = <&qup_i2c14_default>;
739 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
740 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
743 #size-cells = <0>;
749 reg = <0 0x00880000 0 0x4000>;
755 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
756 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
759 #size-cells = <0>;
765 reg = <0 0x00884000 0 0x4000>;
769 pinctrl-0 = <&qup_i2c15_default>;
771 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
775 #size-cells = <0>;
781 reg = <0 0x00884000 0 0x4000>;
787 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
791 #size-cells = <0>;
797 reg = <0 0x00888000 0 0x4000>;
801 pinctrl-0 = <&qup_i2c16_default>;
803 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
807 #size-cells = <0>;
813 reg = <0 0x00888000 0 0x4000>;
819 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
823 #size-cells = <0>;
829 reg = <0 0x0088c000 0 0x4000>;
833 pinctrl-0 = <&qup_i2c17_default>;
835 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
839 #size-cells = <0>;
845 reg = <0 0x0088c000 0 0x4000>;
851 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
855 #size-cells = <0>;
863 reg = <0 0x00890000 0 0x4000>;
869 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
873 #size-cells = <0>;
879 reg = <0 0x00890000 0 0x4000>;
883 pinctrl-0 = <&qup_uart18_default>;
892 reg = <0 0x00894000 0 0x4000>;
896 pinctrl-0 = <&qup_i2c19_default>;
898 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
902 #size-cells = <0>;
908 reg = <0 0x00894000 0 0x4000>;
914 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
918 #size-cells = <0>;
925 reg = <0 0x00900000 0 0x60000>;
939 dma-channel-mask = <0x7e>;
940 iommus = <&apps_smmu 0x5b6 0x0>;
947 reg = <0x0 0x009c0000 0x0 0x6000>;
951 iommus = <&apps_smmu 0x5a3 0>;
959 reg = <0 0x00980000 0 0x4000>;
963 pinctrl-0 = <&qup_i2c0_default>;
965 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
966 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
969 #size-cells = <0>;
975 reg = <0 0x00980000 0 0x4000>;
981 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
982 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
985 #size-cells = <0>;
991 reg = <0 0x00984000 0 0x4000>;
995 pinctrl-0 = <&qup_i2c1_default>;
997 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1001 #size-cells = <0>;
1007 reg = <0 0x00984000 0 0x4000>;
1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1017 #size-cells = <0>;
1023 reg = <0 0x00988000 0 0x4000>;
1027 pinctrl-0 = <&qup_i2c2_default>;
1029 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1033 #size-cells = <0>;
1039 reg = <0 0x00988000 0 0x4000>;
1045 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1049 #size-cells = <0>;
1055 reg = <0 0x0098c000 0 0x4000>;
1059 pinctrl-0 = <&qup_uart3_default_state>;
1070 reg = <0 0x0098c000 0 0x4000>;
1076 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1080 #size-cells = <0>;
1086 reg = <0 0x00990000 0 0x4000>;
1090 pinctrl-0 = <&qup_i2c4_default>;
1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1096 #size-cells = <0>;
1102 reg = <0 0x00990000 0 0x4000>;
1108 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1112 #size-cells = <0>;
1118 reg = <0 0x00994000 0 0x4000>;
1122 pinctrl-0 = <&qup_i2c5_default>;
1124 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1128 #size-cells = <0>;
1134 reg = <0 0x00994000 0 0x4000>;
1140 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1144 #size-cells = <0>;
1150 reg = <0 0x00998000 0 0x4000>;
1154 pinctrl-0 = <&qup_i2c6_default>;
1156 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1160 #size-cells = <0>;
1166 reg = <0 0x00998000 0 0x4000>;
1172 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1176 #size-cells = <0>;
1182 reg = <0 0x00998000 0 0x4000>;
1186 pinctrl-0 = <&qup_uart6_default>;
1195 reg = <0 0x0099c000 0 0x4000>;
1199 pinctrl-0 = <&qup_i2c7_default>;
1201 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1205 #size-cells = <0>;
1211 reg = <0 0x0099c000 0 0x4000>;
1217 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1221 #size-cells = <0>;
1228 reg = <0 0x00a00000 0 0x60000>;
1242 dma-channel-mask = <0xff>;
1243 iommus = <&apps_smmu 0x56 0x0>;
1250 reg = <0x0 0x00ac0000 0x0 0x6000>;
1254 iommus = <&apps_smmu 0x43 0>;
1262 reg = <0 0x00a80000 0 0x4000>;
1266 pinctrl-0 = <&qup_i2c8_default>;
1268 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1269 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1272 #size-cells = <0>;
1278 reg = <0 0x00a80000 0 0x4000>;
1284 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1285 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1288 #size-cells = <0>;
1294 reg = <0 0x00a84000 0 0x4000>;
1298 pinctrl-0 = <&qup_i2c9_default>;
1300 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1304 #size-cells = <0>;
1310 reg = <0 0x00a84000 0 0x4000>;
1316 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1320 #size-cells = <0>;
1326 reg = <0 0x00a88000 0 0x4000>;
1330 pinctrl-0 = <&qup_i2c10_default>;
1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1336 #size-cells = <0>;
1342 reg = <0 0x00a88000 0 0x4000>;
1348 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1352 #size-cells = <0>;
1358 reg = <0 0x00a8c000 0 0x4000>;
1362 pinctrl-0 = <&qup_i2c11_default>;
1364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1368 #size-cells = <0>;
1374 reg = <0 0x00a8c000 0 0x4000>;
1380 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1384 #size-cells = <0>;
1390 reg = <0 0x00a90000 0 0x4000>;
1394 pinctrl-0 = <&qup_i2c12_default>;
1396 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1400 #size-cells = <0>;
1406 reg = <0 0x00a90000 0 0x4000>;
1412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1416 #size-cells = <0>;
1422 reg = <0 0x00a94000 0 0x4000>;
1426 pinctrl-0 = <&qup_i2c13_default>;
1428 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1432 #size-cells = <0>;
1438 reg = <0 0x00a94000 0 0x4000>;
1444 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1448 #size-cells = <0>;
1455 reg = <0 0x010d3000 0 0x1000>;
1462 reg = <0 0x01500000 0 0xa580>;
1469 reg = <0 0x01580000 0 0x1000>;
1476 reg = <0 0x01680000 0 0x1c200>;
1483 reg = <0 0x016e0000 0 0x1f180>;
1490 reg = <0 0x01700000 0 0x33000>;
1497 reg = <0 0x01740000 0 0x1f080>;
1504 reg = <0 0x01c00000 0 0x3000>,
1505 <0 0x60000000 0 0xf1d>,
1506 <0 0x60000f20 0 0xa8>,
1507 <0 0x60001000 0 0x1000>,
1508 <0 0x60100000 0 0x100000>;
1511 linux,pci-domain = <0>;
1512 bus-range = <0x00 0xff>;
1518 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1519 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1532 interrupt-map-mask = <0 0 0 0x7>;
1533 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1534 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1535 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1536 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1557 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1558 <0x100 &apps_smmu 0x1c01 0x1>;
1573 reg = <0 0x01c06000 0 0x2000>;
1587 #clock-cells = <0>;
1590 #phy-cells = <0>;
1597 reg = <0 0x01c08000 0 0x3000>,
1598 <0 0x40000000 0 0xf1d>,
1599 <0 0x40000f20 0 0xa8>,
1600 <0 0x40001000 0 0x1000>,
1601 <0 0x40100000 0 0x100000>;
1605 bus-range = <0x00 0xff>;
1611 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1612 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1617 interrupt-map-mask = <0 0 0 0x7>;
1618 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1619 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1620 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1621 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1640 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1641 <0x100 &apps_smmu 0x1c81 0x1>;
1656 reg = <0 0x01c0e000 0 0x2000>;
1670 #clock-cells = <0>;
1673 #phy-cells = <0>;
1681 reg = <0 0x01d84000 0 0x3000>;
1692 iommus = <&apps_smmu 0xe0 0x0>;
1715 <0 0>,
1716 <0 0>,
1718 <0 0>,
1719 <0 0>,
1720 <0 0>,
1721 <0 0>;
1727 reg = <0 0x01d87000 0 0x1000>;
1734 resets = <&ufs_mem_hc 0>;
1738 #phy-cells = <0>;
1745 reg = <0 0x01dc4000 0 0x24000>;
1748 qcom,ee = <0>;
1750 iommus = <&apps_smmu 0x594 0x0011>,
1751 <&apps_smmu 0x596 0x0011>;
1758 reg = <0 0x01dfa000 0 0x6000>;
1761 iommus = <&apps_smmu 0x594 0x0011>,
1762 <&apps_smmu 0x596 0x0011>;
1763 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1772 iommus = <&apps_smmu 0x5c0 0x0>,
1773 <&apps_smmu 0x5c2 0x0>;
1774 reg = <0 0x01e40000 0 0x8000>,
1775 <0 0x01e50000 0 0x4b20>,
1776 <0 0x01e04000 0 0x23000>;
1783 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1793 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1800 qcom,smem-states = <&ipa_smp2p_out 0>,
1810 reg = <0x0 0x01f40000 0x0 0x40000>;
1816 reg = <0x0 0x1fc0000 0x0 0x30000>;
1821 reg = <0 0x033c0000 0 0x20000>,
1822 <0 0x03550000 0 0x10000>;
1830 gpio-ranges = <&lpass_tlmm 0 0 15>;
1836 reg = <0 0x03d00000 0 0x40000>,
1837 <0 0x03d9e000 0 0x1000>,
1838 <0 0x03d61000 0 0x800>;
1845 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1916 reg = <0 0x03d6a000 0 0x34000>,
1917 <0 0x03de0000 0 0x10000>,
1918 <0 0x0b290000 0 0x10000>;
1945 iommus = <&adreno_smmu 5 0x400>;
1961 reg = <0 0x03d90000 0 0x9000>;
1976 reg = <0 0x03da0000 0 0x20000>;
2013 reg = <0 0x03c40000 0 0xf080>;
2020 reg = <0x0 0x04080000 0x0 0x4040>;
2023 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2038 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2044 qcom,smem-states = <&smp2p_modem_out 0>;
2062 reg = <0 0x05c00000 0 0x4000>;
2065 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2083 qcom,smem-states = <&smp2p_slpi_out 0>;
2104 #size-cells = <0>;
2109 iommus = <&apps_smmu 0x0541 0x0>;
2115 iommus = <&apps_smmu 0x0542 0x0>;
2121 iommus = <&apps_smmu 0x0543 0x0>;
2130 reg = <0 0x08804000 0 0x1000>;
2141 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2144 iommus = <&apps_smmu 0x4a0 0x0>;
2170 reg = <0 0x088e3000 0 0x400>;
2172 #phy-cells = <0>;
2183 reg = <0 0x088e4000 0 0x400>;
2185 #phy-cells = <0>;
2195 reg = <0 0x088e8000 0 0x3000>;
2214 #size-cells = <0>;
2216 port@0 {
2217 reg = <0>;
2241 reg = <0 0x088eb000 0 0x2000>;
2253 #clock-cells = <0>;
2254 #phy-cells = <0>;
2264 reg = <0 0x090c0000 0 0x4200>;
2271 reg = <0 0x09100000 0 0xb4000>;
2278 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2279 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2280 <0 0x09600000 0 0x58000>;
2287 reg = <0 0x0a0c0000 0 0xa180>;
2294 reg = <0 0x0a6f8800 0 0x400>;
2328 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2329 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2334 reg = <0 0x0a600000 0 0xcd00>;
2336 iommus = <&apps_smmu 0x0 0x0>;
2344 #size-cells = <0>;
2346 port@0 {
2347 reg = <0>;
2365 reg = <0 0x0a8f8800 0 0x400>;
2401 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2407 reg = <0 0x0a800000 0 0xcd00>;
2409 iommus = <&apps_smmu 0x20 0x0>;
2419 reg = <0 0x0ae00000 0 0x1000>;
2422 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2423 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2439 iommus = <&apps_smmu 0x820 0x402>;
2449 reg = <0 0x0ae01000 0 0x8f000>,
2450 <0 0x0aeb0000 0 0x2008>;
2473 interrupts = <0>;
2506 #size-cells = <0>;
2508 port@0 {
2509 reg = <0>;
2533 reg = <0 0xae90000 0 0x200>,
2534 <0 0xae90200 0 0x200>,
2535 <0 0xae90400 0 0x600>,
2536 <0 0xae91000 0 0x400>,
2537 <0 0xae91400 0 0x400>;
2559 #sound-dai-cells = <0>;
2568 #size-cells = <0>;
2570 port@0 {
2571 reg = <0>;
2605 reg = <0 0x0ae94000 0 0x400>;
2626 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2635 #size-cells = <0>;
2665 #size-cells = <0>;
2667 port@0 {
2668 reg = <0>;
2684 reg = <0 0x0ae94400 0 0x200>,
2685 <0 0x0ae94600 0 0x280>,
2686 <0 0x0ae94900 0 0x27c>;
2692 #phy-cells = <0>;
2703 reg = <0 0x0ae96000 0 0x400>;
2724 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2733 #size-cells = <0>;
2763 #size-cells = <0>;
2765 port@0 {
2766 reg = <0>;
2782 reg = <0 0x0ae96400 0 0x200>,
2783 <0 0x0ae96600 0 0x280>,
2784 <0 0x0ae96900 0 0x27c>;
2790 #phy-cells = <0>;
2802 reg = <0 0x0af00000 0 0x10000>;
2804 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2805 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2824 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2825 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2836 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2837 <0 0x0c222000 0 0x8>; /* SROT */
2847 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2848 <0 0x0c223000 0 0x8>; /* SROT */
2858 reg = <0 0x0c300000 0 0x400>;
2863 #clock-cells = <0>;
2868 reg = <0 0x0c3f0000 0 0x400>;
2873 reg = <0x0 0x0c440000 0x0 0x1100>,
2874 <0x0 0x0c600000 0x0 0x2000000>,
2875 <0x0 0x0e600000 0x0 0x100000>,
2876 <0x0 0x0e700000 0x0 0xa0000>,
2877 <0x0 0x0c40a000 0x0 0x26000>;
2881 qcom,ee = <0>;
2882 qcom,channel = <0>;
2884 #size-cells = <0>;
2891 reg = <0 0x0f100000 0 0x300000>;
2897 gpio-ranges = <&tlmm 0 0 204>;
3094 reg = <0 0x15000000 0 0x100000>;
3199 reg = <0 0x17300000 0 0x100>;
3202 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3220 qcom,smem-states = <&smp2p_adsp_out 0>;
3240 #size-cells = <0>;
3256 #size-cells = <0>;
3274 #size-cells = <0>;
3276 iommus = <&apps_smmu 0x1801 0x0>;
3278 dai@0 {
3279 reg = <0>;
3299 #sound-dai-cells = <0>;
3310 #size-cells = <0>;
3315 iommus = <&apps_smmu 0x1803 0x0>;
3321 iommus = <&apps_smmu 0x1804 0x0>;
3327 iommus = <&apps_smmu 0x1805 0x0>;
3338 redistributor-stride = <0 0x20000>;
3339 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3340 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3348 ranges = <0 0 0 0x20000000>;
3349 reg = <0x0 0x17c20000 0x0 0x1000>;
3353 frame-number = <0>;
3356 reg = <0x17c21000 0x1000>,
3357 <0x17c22000 0x1000>;
3363 reg = <0x17c23000 0x1000>;
3370 reg = <0x17c25000 0x1000>;
3377 reg = <0x17c27000 0x1000>;
3384 reg = <0x17c29000 0x1000>;
3391 reg = <0x17c2b000 0x1000>;
3398 reg = <0x17c2d000 0x1000>;
3406 reg = <0x0 0x18200000 0x0 0x10000>,
3407 <0x0 0x18210000 0x0 0x10000>,
3408 <0x0 0x18220000 0x0 0x10000>;
3409 reg-names = "drv-0", "drv-1", "drv-2";
3413 qcom,tcs-offset = <0xd00>;
3416 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3483 reg = <0 0x18591000 0 0x1000>,
3484 <0 0x18592000 0 0x1000>,
3485 <0 0x18593000 0 0x1000>;
3491 interrupt-names = "dcvsh-irq-0",
3504 reg = <0 0x98900000 0 0x1400000>;
3507 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3521 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3527 qcom,smem-states = <&smp2p_cdsp_out 0>;
3548 #size-cells = <0>;
3553 iommus = <&apps_smmu 0x2161 0x0400>,
3554 <&apps_smmu 0x1181 0x0420>;
3560 iommus = <&apps_smmu 0x2162 0x0400>,
3561 <&apps_smmu 0x1182 0x0420>;
3567 iommus = <&apps_smmu 0x2163 0x0400>,
3568 <&apps_smmu 0x1183 0x0420>;
3574 iommus = <&apps_smmu 0x2164 0x0400>,
3575 <&apps_smmu 0x1184 0x0420>;
3581 iommus = <&apps_smmu 0x2165 0x0400>,
3582 <&apps_smmu 0x1185 0x0420>;
3588 iommus = <&apps_smmu 0x2166 0x0400>,
3589 <&apps_smmu 0x1186 0x0420>;
3595 iommus = <&apps_smmu 0x2167 0x0400>,
3596 <&apps_smmu 0x1187 0x0420>;
3602 iommus = <&apps_smmu 0x2168 0x0400>,
3603 <&apps_smmu 0x1188 0x0420>;
4145 thermal-sensors = <&tsens0 0>;
4200 thermal-sensors = <&tsens1 0>;