Lines Matching +full:0 +full:x0e700000
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
131 reg = <0x0 0x400>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
153 reg = <0x0 0x500>;
157 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x600>;
197 reg = <0x0 0x700>;
255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
258 arm,psci-suspend-param = <0x40000004>;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
268 arm,psci-suspend-param = <0x40000004>;
277 CLUSTER_SLEEP_0: cluster-sleep-0 {
279 arm,psci-suspend-param = <0x4100c244>;
296 reg = <0x0 0x80000000 0x0 0x0>;
433 #power-domain-cells = <0>;
439 #power-domain-cells = <0>;
445 #power-domain-cells = <0>;
451 #power-domain-cells = <0>;
457 #power-domain-cells = <0>;
463 #power-domain-cells = <0>;
469 #power-domain-cells = <0>;
475 #power-domain-cells = <0>;
481 #power-domain-cells = <0>;
492 reg = <0 0x85700000 0 0x600000>;
497 reg = <0 0x85e00000 0 0x100000>;
502 reg = <0 0x85fc0000 0 0x20000>;
508 reg = <0 0x85fe0000 0 0x20000>;
513 reg = <0 0x8ab00000 0 0x500000>;
518 reg = <0 0x8b000000 0 0x7e00000>;
523 reg = <0 0x92e00000 0 0x500000>;
528 reg = <0 0x93300000 0 0x100000>;
533 reg = <0 0x93400000 0 0x800000>;
538 reg = <0 0x93c00000 0 0x200000>;
543 reg = <0 0x93e00000 0 0x1e00000>;
548 reg = <0 0x95c00000 0 0x10000>;
553 reg = <0 0x95c10000 0 0x5000>;
558 reg = <0 0x95c15000 0 0x2000>;
563 reg = <0 0x97b00000 0 0x100000>;
568 reg = <0 0x9e400000 0 0x1400000>;
578 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
581 soc: soc@0 {
584 ranges = <0 0 0 0 0x10 0>;
585 dma-ranges = <0 0 0 0 0x10 0>;
590 reg = <0 0x00100000 0 0x1f0000>;
604 reg = <0 0x00784000 0 0x1000>;
609 reg = <0x1eb 0x1>;
616 reg = <0 0x007c4000 0 0x1000>,
617 <0 0x007c5000 0 0x1000>,
618 <0 0x007c8000 0 0x8000>;
631 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
632 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
636 iommus = <&apps_smmu 0x140 0xf>;
639 pinctrl-0 = <&sdc1_state_on>;
684 reg = <0 0x00800000 0 0x60000>;
699 dma-channel-mask = <0xfa>;
700 iommus = <&apps_smmu 0x16 0x0>;
706 reg = <0 0x008c0000 0 0x6000>;
710 iommus = <&apps_smmu 0x3 0x0>;
714 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
720 reg = <0 0x00880000 0 0x4000>;
724 pinctrl-0 = <&qup_i2c0_default>;
727 #size-cells = <0>;
729 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
730 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
731 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
733 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
734 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
741 reg = <0 0x00884000 0 0x4000>;
745 pinctrl-0 = <&qup_i2c1_default>;
748 #size-cells = <0>;
750 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
751 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
752 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
754 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
762 reg = <0 0x00888000 0 0x4000>;
766 pinctrl-0 = <&qup_i2c2_default>;
769 #size-cells = <0>;
771 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
772 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
773 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
775 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
783 reg = <0 0x0088c000 0 0x4000>;
787 pinctrl-0 = <&qup_i2c3_default>;
790 #size-cells = <0>;
792 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
793 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
794 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
796 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
804 reg = <0 0x00890000 0 0x4000>;
808 pinctrl-0 = <&qup_i2c4_default>;
811 #size-cells = <0>;
813 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
814 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
815 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
817 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
825 reg = <0 0x00894000 0 0x4000>;
829 pinctrl-0 = <&qup_i2c5_default>;
832 #size-cells = <0>;
834 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
835 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
836 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
838 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
846 reg = <0 0x00898000 0 0x4000>;
850 pinctrl-0 = <&qup_i2c6_default>;
853 #size-cells = <0>;
855 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
856 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
857 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
859 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
867 reg = <0 0x0089c000 0 0x4000>;
871 pinctrl-0 = <&qup_i2c7_default>;
874 #size-cells = <0>;
876 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
877 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
878 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
880 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
890 reg = <0 0x00a00000 0 0x60000>;
905 dma-channel-mask = <0xfa>;
906 iommus = <&apps_smmu 0x6d6 0x0>;
912 reg = <0 0x00ac0000 0 0x6000>;
916 iommus = <&apps_smmu 0x6c3 0x0>;
920 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
926 reg = <0 0x00a80000 0 0x4000>;
930 pinctrl-0 = <&qup_i2c8_default>;
933 #size-cells = <0>;
935 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
936 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
937 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
939 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
940 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
947 reg = <0 0x00a84000 0 0x4000>;
951 pinctrl-0 = <&qup_i2c9_default>;
954 #size-cells = <0>;
956 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
957 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
958 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
960 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
968 reg = <0 0x00a88000 0 0x4000>;
972 pinctrl-0 = <&qup_i2c10_default>;
975 #size-cells = <0>;
977 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
978 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
979 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
981 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
989 reg = <0 0x00a8c000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c11_default>;
996 #size-cells = <0>;
998 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
999 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1000 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1002 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1010 reg = <0 0x00a90000 0 0x4000>;
1014 pinctrl-0 = <&qup_i2c12_default>;
1017 #size-cells = <0>;
1019 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1020 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1021 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1023 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1031 reg = <0 0x00a94000 0 0x4000>;
1035 pinctrl-0 = <&qup_i2c13_default>;
1038 #size-cells = <0>;
1040 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1041 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1042 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1044 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1052 reg = <0 0x00a98000 0 0x4000>;
1056 pinctrl-0 = <&qup_i2c14_default>;
1059 #size-cells = <0>;
1061 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1062 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1063 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1065 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1073 reg = <0 0x00a9c000 0 0x4000>;
1077 pinctrl-0 = <&qup_i2c15_default>;
1080 #size-cells = <0>;
1082 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1083 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1084 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1086 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1095 reg = <0 0x01380000 0 0x27200>;
1102 reg = <0 0x014e0000 0 0x400>;
1109 reg = <0 0x01500000 0 0x5080>;
1116 reg = <0 0x01620000 0 0x18080>;
1123 reg = <0 0x016e0000 0 0x15080>;
1130 reg = <0 0x01700000 0 0x1f300>;
1137 reg = <0 0x01740000 0 0x1c100>;
1144 reg = <0 0x03400000 0 0xc00000>;
1150 gpio-ranges = <&tlmm 0 0 151>;
1286 reg = <0 0x088e2000 0 0x400>;
1287 #phy-cells = <0>;
1302 reg = <0 0x0a6f8800 0 0x400>;
1334 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1335 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1342 reg = <0 0x0a600000 0 0xcd00>;
1344 iommus = <&apps_smmu 0x740 0>;
1354 reg = <0 0x0b220000 0 0x30000>;
1355 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1365 reg = <0 0x0c440000 0 0x1100>,
1366 <0 0x0c600000 0 0x2000000>,
1367 <0 0x0e600000 0 0x100000>,
1368 <0 0x0e700000 0 0xa0000>,
1369 <0 0x0c40a000 0 0x26000>;
1373 qcom,ee = <0>;
1374 qcom,channel = <0>;
1376 #size-cells = <0>;
1383 reg = <0 0x0ae00000 0 0x1000>;
1396 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
1397 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
1400 iommus = <&apps_smmu 0x880 0x8>,
1401 <&apps_smmu 0xc80 0x8>;
1411 reg = <0 0x0ae01000 0 0x8f000>,
1412 <0 0x0aeb0000 0 0x2008>;
1428 interrupts = <0>;
1432 #size-cells = <0>;
1434 port@0 {
1435 reg = <0>;
1477 reg = <0 0x0ae94000 0 0x400>;
1497 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1506 #size-cells = <0>;
1512 #size-cells = <0>;
1514 port@0 {
1515 reg = <0>;
1531 reg = <0 0x0ae94400 0 0x200>,
1532 <0 0x0ae94600 0 0x280>,
1533 <0 0x0ae94a00 0 0x1e0>;
1539 #phy-cells = <0>;
1551 reg = <0 0x0ae96000 0 0x400>;
1571 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1579 #size-cells = <0>;
1585 #size-cells = <0>;
1587 port@0 {
1588 reg = <0>;
1604 reg = <0 0x0ae96400 0 0x200>,
1605 <0 0x0ae96600 0 0x280>,
1606 <0 0x0ae96a00 0 0x10e>;
1612 #phy-cells = <0>;
1624 reg = <0 0x0af00000 0 0x10000>;
1628 <&mdss_dsi0_phy 0>,
1630 <&mdss_dsi1_phy 0>,
1632 <0>,
1633 <0>;
1650 reg = <0 0x15000000 0 0x80000>;
1722 reg = <0 0x17900000 0 0xd080>;
1729 reg = <0 0x179c0000 0 0x10000>,
1730 <0 0x179d0000 0 0x10000>,
1731 <0 0x179e0000 0 0x10000>;
1732 reg-names = "drv-0", "drv-1", "drv-2";
1737 qcom,tcs-offset = <0xd00>;
1809 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1810 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1818 reg = <0 0x17d41000 0 0x1400>;
1828 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;