| /linux/arch/s390/include/asm/ |
| H A D | lowcore.h | 23 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
32 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
33 __u32 ipl_parmblock_ptr; /* 0x0014 */
34 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
35 __u32 ext_params; /* 0x0080 */
38 __u16 ext_cpu_addr; /* 0x0084 */
39 __u16 ext_int_code; /* 0x0086 */
43 __u32 svc_int_code; /* 0x0088 */
46 __u16 pgm_ilc; /* 0x008c */
47 __u16 pgm_code; /* 0x008e */
[all …]
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| /linux/drivers/tty/serial/ |
| H A D | dz.h | 18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
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| /linux/arch/m68k/include/asm/ |
| H A D | mcfdma.h | 21 #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
22 #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
24 #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
25 #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
27 #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
28 #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
33 #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
34 #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
35 #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
36 #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
[all …]
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| H A D | mcfpit.h | 18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
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| /linux/drivers/media/dvb-frontends/ |
| H A D | atbm8830_priv.h | 19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
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| /linux/arch/arm/mach-omap2/ |
| H A D | prm33xx.h | 14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
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| H A D | prcm-common.h | 22 #define OCP_MOD 0x000
23 #define MPU_MOD 0x100
24 #define CORE_MOD 0x200
25 #define GFX_MOD 0x300
26 #define WKUP_MOD 0x400
27 #define PLL_MOD 0x500
32 #define OMAP24XX_DSP_MOD 0x800
34 #define OMAP2430_MDM_MOD 0xc00
37 #define OMAP3430_IVA2_MOD -0x800
40 #define OMAP3430_DSS_MOD 0x600
[all …]
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| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | rvu_reg.c | 30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | rcar-gen4-pci-ep.yaml | 100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
103 <0 0xfe000000 0 0x400000>;
|
| H A D | rcar-gen4-pci-host.yaml | 98 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
99 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
100 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
101 <0 0xfe000000 0 0x400000>;
117 bus-range = <0x00 0xff>;
119 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
120 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
121 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /linux/drivers/misc/ |
| H A D | tifm_7xx1.c | 15 #define TIFM_IRQ_ENABLE 0x80000000
19 #define TIFM_IRQ_SETALL 0xffffffff
44 if (irq_status == 0 || irq_status == (~0)) { in tifm_7xx1_isr()
52 for (cnt = 0; cnt < fm->num_sockets; cnt++) { in tifm_7xx1_isr()
83 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_toggle_sock_power()
95 return 0; in tifm_7xx1_toggle_sock_power()
105 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, in tifm_7xx1_toggle_sock_power()
147 fm->socket_change_set = 0; in tifm_7xx1_switch_media()
157 for (cnt = 0; cnt < fm->num_sockets; cnt++) { in tifm_7xx1_switch_media()
171 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_switch_media()
[all …]
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| /linux/arch/powerpc/lib/ |
| H A D | copypage_power7.S | 14 * instructions. We use a stream ID of 0 for the load side and
22 lis r7,0x0E01 /* depth=7
25 lis r7,0x0E00 /* depth=7 */
26 ori r7,r7,0x1000 /* units/cachelines=32 */
39 cmpwi r3,0
61 1: lvx v7,0,r4
70 stvx v7,0,r3
99 1: ld r0,0(r4)
116 std r0,0(r3)
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| /linux/include/linux/mfd/wm8350/ |
| H A D | audio.h | 13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
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| /linux/drivers/net/can/softing/ |
| H A D | softing.h | 105 #define DPRAM_RX 0x0000
108 #define DPRAM_RX_RD 0x0201 /* uint8_t */
109 #define DPRAM_RX_WR 0x0205 /* uint8_t */
110 #define DPRAM_RX_LOST 0x0207 /* uint8_t */
112 #define DPRAM_FCT_PARAM 0x0300 /* int16_t [20] */
113 #define DPRAM_FCT_RESULT 0x0328 /* int16_t */
114 #define DPRAM_FCT_HOST 0x032b /* uint16_t */
116 #define DPRAM_INFO_BUSSTATE 0x0331 /* uint16_t */
117 #define DPRAM_INFO_BUSSTATE2 0x0335 /* uint16_t */
118 #define DPRAM_INFO_ERRSTATE 0x0339 /* uint16_t */
[all …]
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| /linux/sound/pci/cs46xx/ |
| H A D | dsp_spos.h | 18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]
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| /linux/drivers/block/ |
| H A D | swim_asm.S | 17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
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| /linux/include/uapi/linux/ |
| H A D | in6.h | 83 #define IPV6_FL_A_GET 0
92 #define IPV6_FL_S_NONE 0
107 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
108 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
111 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
112 #define IPV6_PRIORITY_FILLER 0x0100
113 #define IPV6_PRIORITY_UNATTENDED 0x0200
114 #define IPV6_PRIORITY_RESERVED1 0x0300
115 #define IPV6_PRIORITY_BULK 0x0400
116 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
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| /linux/include/linux/ |
| H A D | brcmphy.h | 12 #define PHY_ID_BCM50610 0x0143bd60
13 #define PHY_ID_BCM50610M 0x0143bd70
14 #define PHY_ID_BCM5221 0x004061e0
15 #define PHY_ID_BCM5241 0x0143bc30
16 #define PHY_ID_BCMAC131 0x0143bc70
17 #define PHY_ID_BCM5481 0x0143bca0
18 #define PHY_ID_BCM5395 0x0143bcf0
19 #define PHY_ID_BCM53125 0x03625f20
20 #define PHY_ID_BCM53128 0x03625e10
21 #define PHY_ID_BCM54810 0x03625d00
[all …]
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| /linux/drivers/pcmcia/ |
| H A D | tcic.h | 33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
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| /linux/arch/arm/mach-imx/ |
| H A D | tzic.c | 28 #define TZIC_INTCNTL 0x0000 /* Control register */
29 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
30 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
31 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
32 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
33 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
34 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
35 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
36 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
37 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
[all …]
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779f0.dtsi | 17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
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| /linux/drivers/media/platform/st/sti/bdisp/ |
| H A D | bdisp-reg.h | 8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
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| /linux/drivers/soc/fsl/qbman/ |
| H A D | bman_ccsr.c | 37 #define REG_FBPR_FPC 0x0800
38 #define REG_ECSR 0x0a00
39 #define REG_ECIR 0x0a04
40 #define REG_EADR 0x0a08
41 #define REG_EDATA(n) (0x0a10 + ((n) * 0x04))
42 #define REG_SBEC(n) (0x0a80 + ((n) * 0x04))
43 #define REG_IP_REV_1 0x0bf8
44 #define REG_IP_REV_2 0x0bfc
45 #define REG_FBPR_BARE 0x0c00
46 #define REG_FBPR_BAR 0x0c04
[all …]
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| /linux/drivers/media/pci/smipcie/ |
| H A D | smipcie.h | 31 #define MSI_CONTROL_REG_BASE 0x0800
32 #define SYSTEM_CONTROL_REG_BASE 0x0880
33 #define PCIE_EP_DEBUG_REG_BASE 0x08C0
34 #define IR_CONTROL_REG_BASE 0x0900
35 #define I2C_A_CONTROL_REG_BASE 0x0940
36 #define I2C_B_CONTROL_REG_BASE 0x0980
37 #define ATV_PORTA_CONTROL_REG_BASE 0x09C0
38 #define DTV_PORTA_CONTROL_REG_BASE 0x0A00
39 #define AES_PORTA_CONTROL_REG_BASE 0x0A80
40 #define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
[all …]
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| /linux/drivers/clk/bcm/ |
| H A D | clk-bcm281xx.c | 16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .trig = TRIGGER(0x0e04, 0),
18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .sel = SELECTOR(0x0a04, 0, 2),
48 .div = DIVIDER(0x0a04, 3, 4),
49 .trig = TRIGGER(0x0a40, 0),
[all …]
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