1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * mcfpit.h -- ColdFire internal PIT timer support defines. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 849148020SSam Ravnborg */ 949148020SSam Ravnborg 1049148020SSam Ravnborg /****************************************************************************/ 1149148020SSam Ravnborg #ifndef mcfpit_h 1249148020SSam Ravnborg #define mcfpit_h 1349148020SSam Ravnborg /****************************************************************************/ 1449148020SSam Ravnborg 1549148020SSam Ravnborg /* 16f317c71aSGreg Ungerer * Define the PIT timer register address offsets. 1749148020SSam Ravnborg */ 1849148020SSam Ravnborg #define MCFPIT_PCSR 0x0 /* PIT control register */ 1949148020SSam Ravnborg #define MCFPIT_PMR 0x2 /* PIT modulus register */ 2049148020SSam Ravnborg #define MCFPIT_PCNTR 0x4 /* PIT count register */ 2149148020SSam Ravnborg 2249148020SSam Ravnborg /* 2349148020SSam Ravnborg * Bit definitions for the PIT Control and Status register. 2449148020SSam Ravnborg */ 2549148020SSam Ravnborg #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ 2649148020SSam Ravnborg #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ 2749148020SSam Ravnborg #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ 2849148020SSam Ravnborg #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ 2949148020SSam Ravnborg #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ 3049148020SSam Ravnborg #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ 3149148020SSam Ravnborg #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ 3249148020SSam Ravnborg #define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ 3349148020SSam Ravnborg #define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ 3449148020SSam Ravnborg #define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ 3549148020SSam Ravnborg #define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ 3649148020SSam Ravnborg #define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ 3749148020SSam Ravnborg #define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ 3849148020SSam Ravnborg #define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ 3949148020SSam Ravnborg #define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ 4049148020SSam Ravnborg #define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ 4149148020SSam Ravnborg #define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ 4249148020SSam Ravnborg #define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ 4349148020SSam Ravnborg #define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ 4449148020SSam Ravnborg #define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ 4549148020SSam Ravnborg #define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ 4649148020SSam Ravnborg #define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ 4749148020SSam Ravnborg #define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ 4849148020SSam Ravnborg #define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ 4949148020SSam Ravnborg 5049148020SSam Ravnborg /****************************************************************************/ 5149148020SSam Ravnborg #endif /* mcfpit_h */ 52