1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
4c1017a4cSJaroslav Kysela * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
51da177e4SLinus Torvalds */
61da177e4SLinus Torvalds
71da177e4SLinus Torvalds /*
81da177e4SLinus Torvalds * 2002-07 Benny Sjostrand benny@hostmobility.com
91da177e4SLinus Torvalds */
101da177e4SLinus Torvalds
111da177e4SLinus Torvalds #ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
121da177e4SLinus Torvalds #ifndef __DSP_SPOS_H__
131da177e4SLinus Torvalds #define __DSP_SPOS_H__
141da177e4SLinus Torvalds
151da177e4SLinus Torvalds #define DSP_MAX_SYMBOLS 1024
161da177e4SLinus Torvalds #define DSP_MAX_MODULES 64
171da177e4SLinus Torvalds
181da177e4SLinus Torvalds #define DSP_CODE_BYTE_SIZE 0x00007000UL
191da177e4SLinus Torvalds #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
201da177e4SLinus Torvalds #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
211da177e4SLinus Torvalds #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
221da177e4SLinus Torvalds #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
231da177e4SLinus Torvalds #define DSP_CODE_BYTE_OFFSET 0x00020000UL
241da177e4SLinus Torvalds
251da177e4SLinus Torvalds #define WIDE_INSTR_MASK 0x0040
261da177e4SLinus Torvalds #define WIDE_LADD_INSTR_MASK 0x0380
271da177e4SLinus Torvalds
281da177e4SLinus Torvalds /* this instruction types
291da177e4SLinus Torvalds needs to be reallocated when load
301da177e4SLinus Torvalds code into DSP */
313d19f804STakashi Iwai enum wide_opcode {
321da177e4SLinus Torvalds WIDE_FOR_BEGIN_LOOP = 0x20,
331da177e4SLinus Torvalds WIDE_FOR_BEGIN_LOOP2,
341da177e4SLinus Torvalds
351da177e4SLinus Torvalds WIDE_COND_GOTO_ADDR = 0x30,
361da177e4SLinus Torvalds WIDE_COND_GOTO_CALL,
371da177e4SLinus Torvalds
381da177e4SLinus Torvalds WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
391da177e4SLinus Torvalds WIDE_TBEQ_COND_CALL_ADDR,
401da177e4SLinus Torvalds WIDE_TBEQ_NCOND_GOTO_ADDR,
411da177e4SLinus Torvalds WIDE_TBEQ_NCOND_CALL_ADDR,
421da177e4SLinus Torvalds WIDE_TBEQ_COND_GOTO1_ADDR,
431da177e4SLinus Torvalds WIDE_TBEQ_COND_CALL1_ADDR,
441da177e4SLinus Torvalds WIDE_TBEQ_NCOND_GOTOI_ADDR,
451da177e4SLinus Torvalds WIDE_TBEQ_NCOND_CALL1_ADDR,
463d19f804STakashi Iwai };
471da177e4SLinus Torvalds
481da177e4SLinus Torvalds /* SAMPLE segment */
491da177e4SLinus Torvalds #define VARI_DECIMATE_BUF1 0x0000
501da177e4SLinus Torvalds #define WRITE_BACK_BUF1 0x0400
511da177e4SLinus Torvalds #define CODEC_INPUT_BUF1 0x0500
521da177e4SLinus Torvalds #define PCM_READER_BUF1 0x0600
531da177e4SLinus Torvalds #define SRC_DELAY_BUF1 0x0680
541da177e4SLinus Torvalds #define VARI_DECIMATE_BUF0 0x0780
551da177e4SLinus Torvalds #define SRC_OUTPUT_BUF1 0x07A0
561da177e4SLinus Torvalds #define ASYNC_IP_OUTPUT_BUFFER1 0x0A00
571da177e4SLinus Torvalds #define OUTPUT_SNOOP_BUFFER 0x0B00
581da177e4SLinus Torvalds #define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
591da177e4SLinus Torvalds #define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
601da177e4SLinus Torvalds #define MIX_SAMPLE_BUF1 0x1400
611da177e4SLinus Torvalds #define MIX_SAMPLE_BUF2 0x2E80
621da177e4SLinus Torvalds #define MIX_SAMPLE_BUF3 0x2F00
631da177e4SLinus Torvalds #define MIX_SAMPLE_BUF4 0x2F80
641da177e4SLinus Torvalds #define MIX_SAMPLE_BUF5 0x3000
651da177e4SLinus Torvalds
661da177e4SLinus Torvalds /* Task stack address */
671da177e4SLinus Torvalds #define HFG_STACK 0x066A
681da177e4SLinus Torvalds #define FG_STACK 0x066E
691da177e4SLinus Torvalds #define BG_STACK 0x068E
701da177e4SLinus Torvalds
711da177e4SLinus Torvalds /* SCB's addresses */
721da177e4SLinus Torvalds #define SPOSCB_ADDR 0x070
731da177e4SLinus Torvalds #define BG_TREE_SCB_ADDR 0x635
741da177e4SLinus Torvalds #define NULL_SCB_ADDR 0x000
751da177e4SLinus Torvalds #define TIMINGMASTER_SCB_ADDR 0x010
761da177e4SLinus Torvalds #define CODECOUT_SCB_ADDR 0x020
771da177e4SLinus Torvalds #define PCMREADER_SCB_ADDR 0x030
781da177e4SLinus Torvalds #define WRITEBACK_SCB_ADDR 0x040
791da177e4SLinus Torvalds #define CODECIN_SCB_ADDR 0x080
801da177e4SLinus Torvalds #define MASTERMIX_SCB_ADDR 0x090
811da177e4SLinus Torvalds #define SRCTASK_SCB_ADDR 0x0A0
821da177e4SLinus Torvalds #define VARIDECIMATE_SCB_ADDR 0x0B0
831da177e4SLinus Torvalds #define PCMSERIALIN_SCB_ADDR 0x0C0
841da177e4SLinus Torvalds #define FG_TASK_HEADER_ADDR 0x600
851da177e4SLinus Torvalds #define ASYNCTX_SCB_ADDR 0x0E0
861da177e4SLinus Torvalds #define ASYNCRX_SCB_ADDR 0x0F0
871da177e4SLinus Torvalds #define SRCTASKII_SCB_ADDR 0x100
881da177e4SLinus Torvalds #define OUTPUTSNOOP_SCB_ADDR 0x110
891da177e4SLinus Torvalds #define PCMSERIALINII_SCB_ADDR 0x120
901da177e4SLinus Torvalds #define SPIOWRITE_SCB_ADDR 0x130
911da177e4SLinus Torvalds #define REAR_CODECOUT_SCB_ADDR 0x140
921da177e4SLinus Torvalds #define OUTPUTSNOOPII_SCB_ADDR 0x150
931da177e4SLinus Torvalds #define PCMSERIALIN_PCM_SCB_ADDR 0x160
941da177e4SLinus Torvalds #define RECORD_MIXER_SCB_ADDR 0x170
951da177e4SLinus Torvalds #define REAR_MIXER_SCB_ADDR 0x180
961da177e4SLinus Torvalds #define CLFE_MIXER_SCB_ADDR 0x190
971da177e4SLinus Torvalds #define CLFE_CODEC_SCB_ADDR 0x1A0
981da177e4SLinus Torvalds
991da177e4SLinus Torvalds /* hyperforground SCB's*/
1001da177e4SLinus Torvalds #define HFG_TREE_SCB 0xBA0
1011da177e4SLinus Torvalds #define SPDIFI_SCB_INST 0xBB0
1021da177e4SLinus Torvalds #define SPDIFO_SCB_INST 0xBC0
1031da177e4SLinus Torvalds #define WRITE_BACK_SPB 0x0D0
1041da177e4SLinus Torvalds
1051da177e4SLinus Torvalds /* offsets */
1061da177e4SLinus Torvalds #define AsyncCIOFIFOPointer 0xd
1071da177e4SLinus Torvalds #define SPDIFOFIFOPointer 0xd
1081da177e4SLinus Torvalds #define SPDIFIFIFOPointer 0xd
1091da177e4SLinus Torvalds #define TCBData 0xb
1101da177e4SLinus Torvalds #define HFGFlags 0xa
1111da177e4SLinus Torvalds #define TCBContextBlk 0x10
1121da177e4SLinus Torvalds #define AFGTxAccumPhi 0x4
1131da177e4SLinus Torvalds #define SCBsubListPtr 0x9
1141da177e4SLinus Torvalds #define SCBfuncEntryPtr 0xA
1151da177e4SLinus Torvalds #define SRCCorPerGof 0x2
1161da177e4SLinus Torvalds #define SRCPhiIncr6Int26Frac 0xd
1171da177e4SLinus Torvalds #define SCBVolumeCtrl 0xe
1181da177e4SLinus Torvalds
1191da177e4SLinus Torvalds /* conf */
1201da177e4SLinus Torvalds #define UseASER1Input 1
1211da177e4SLinus Torvalds
1221da177e4SLinus Torvalds
1231da177e4SLinus Torvalds
1241da177e4SLinus Torvalds /*
1251da177e4SLinus Torvalds * The following defines are for the flags in the rsConfig01/23 registers of
1261da177e4SLinus Torvalds * the SP.
1271da177e4SLinus Torvalds */
1281da177e4SLinus Torvalds
1291da177e4SLinus Torvalds #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
1301da177e4SLinus Torvalds #define RSCONFIG_MODULO_16 0x00000001L
1311da177e4SLinus Torvalds #define RSCONFIG_MODULO_32 0x00000002L
1321da177e4SLinus Torvalds #define RSCONFIG_MODULO_64 0x00000003L
1331da177e4SLinus Torvalds #define RSCONFIG_MODULO_128 0x00000004L
1341da177e4SLinus Torvalds #define RSCONFIG_MODULO_256 0x00000005L
1351da177e4SLinus Torvalds #define RSCONFIG_MODULO_512 0x00000006L
1361da177e4SLinus Torvalds #define RSCONFIG_MODULO_1024 0x00000007L
1371da177e4SLinus Torvalds #define RSCONFIG_MODULO_4 0x00000008L
1381da177e4SLinus Torvalds #define RSCONFIG_MODULO_8 0x00000009L
1391da177e4SLinus Torvalds #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
1401da177e4SLinus Torvalds #define RSCONFIG_SAMPLE_8MONO 0x00000000L
1411da177e4SLinus Torvalds #define RSCONFIG_SAMPLE_8STEREO 0x00000040L
1421da177e4SLinus Torvalds #define RSCONFIG_SAMPLE_16MONO 0x00000080L
1431da177e4SLinus Torvalds #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
1441da177e4SLinus Torvalds #define RSCONFIG_UNDERRUN_ZERO 0x00004000L
1451da177e4SLinus Torvalds #define RSCONFIG_DMA_TO_HOST 0x00008000L
1461da177e4SLinus Torvalds #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
1471da177e4SLinus Torvalds #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
1481da177e4SLinus Torvalds #define RSCONFIG_DMA_ENABLE 0x20000000L
1491da177e4SLinus Torvalds #define RSCONFIG_PRIORITY_MASK 0xC0000000L
1501da177e4SLinus Torvalds #define RSCONFIG_PRIORITY_HIGH 0x00000000L
1511da177e4SLinus Torvalds #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
1521da177e4SLinus Torvalds #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
1531da177e4SLinus Torvalds #define RSCONFIG_PRIORITY_LOW 0xC0000000L
1541da177e4SLinus Torvalds #define RSCONFIG_STREAM_NUM_SHIFT 16L
1551da177e4SLinus Torvalds #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
1561da177e4SLinus Torvalds
1571da177e4SLinus Torvalds /* SP constants */
1581da177e4SLinus Torvalds #define FG_INTERVAL_TIMER_PERIOD 0x0051
1591da177e4SLinus Torvalds #define BG_INTERVAL_TIMER_PERIOD 0x0100
1601da177e4SLinus Torvalds
1611da177e4SLinus Torvalds
1621da177e4SLinus Torvalds /* Only SP accessible registers */
1631da177e4SLinus Torvalds #define SP_ASER_COUNTDOWN 0x8040
1641da177e4SLinus Torvalds #define SP_SPDOUT_FIFO 0x0108
1651da177e4SLinus Torvalds #define SP_SPDIN_MI_FIFO 0x01E0
1661da177e4SLinus Torvalds #define SP_SPDIN_D_FIFO 0x01F0
1671da177e4SLinus Torvalds #define SP_SPDIN_STATUS 0x8048
1681da177e4SLinus Torvalds #define SP_SPDIN_CONTROL 0x8049
1691da177e4SLinus Torvalds #define SP_SPDIN_FIFOPTR 0x804A
1701da177e4SLinus Torvalds #define SP_SPDOUT_STATUS 0x804C
1711da177e4SLinus Torvalds #define SP_SPDOUT_CONTROL 0x804D
1721da177e4SLinus Torvalds #define SP_SPDOUT_CSUV 0x808E
1731da177e4SLinus Torvalds
_wrap_all_bits(u8 val)1743d19f804STakashi Iwai static inline u8 _wrap_all_bits (u8 val)
1753d19f804STakashi Iwai {
1761da177e4SLinus Torvalds u8 wrapped;
1771da177e4SLinus Torvalds
1781da177e4SLinus Torvalds /* wrap all 8 bits */
1791da177e4SLinus Torvalds wrapped =
1801da177e4SLinus Torvalds ((val & 0x1 ) << 7) |
1811da177e4SLinus Torvalds ((val & 0x2 ) << 5) |
1821da177e4SLinus Torvalds ((val & 0x4 ) << 3) |
1831da177e4SLinus Torvalds ((val & 0x8 ) << 1) |
1841da177e4SLinus Torvalds ((val & 0x10) >> 1) |
1851da177e4SLinus Torvalds ((val & 0x20) >> 3) |
1861da177e4SLinus Torvalds ((val & 0x40) >> 5) |
1871da177e4SLinus Torvalds ((val & 0x80) >> 7);
1881da177e4SLinus Torvalds
1891da177e4SLinus Torvalds return wrapped;
1901da177e4SLinus Torvalds }
1911da177e4SLinus Torvalds
cs46xx_dsp_spos_update_scb(struct snd_cs46xx * chip,struct dsp_scb_descriptor * scb)1923d19f804STakashi Iwai static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
1933d19f804STakashi Iwai struct dsp_scb_descriptor * scb)
1941da177e4SLinus Torvalds {
1951da177e4SLinus Torvalds /* update nextSCB and subListPtr in SCB */
1961da177e4SLinus Torvalds snd_cs46xx_poke(chip,
1971da177e4SLinus Torvalds (scb->address + SCBsubListPtr) << 2,
1981da177e4SLinus Torvalds (scb->sub_list_ptr->address << 0x10) |
1991da177e4SLinus Torvalds (scb->next_scb_ptr->address));
20041116e92STakashi Iwai scb->updated = 1;
2011da177e4SLinus Torvalds }
2021da177e4SLinus Torvalds
cs46xx_dsp_scb_set_volume(struct snd_cs46xx * chip,struct dsp_scb_descriptor * scb,u16 left,u16 right)2033d19f804STakashi Iwai static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
2043d19f804STakashi Iwai struct dsp_scb_descriptor * scb,
2053d19f804STakashi Iwai u16 left, u16 right)
2063d19f804STakashi Iwai {
2071da177e4SLinus Torvalds unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
2081da177e4SLinus Torvalds
2091da177e4SLinus Torvalds snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
2101da177e4SLinus Torvalds snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
21141116e92STakashi Iwai scb->volume_set = 1;
21241116e92STakashi Iwai scb->volume[0] = left;
21341116e92STakashi Iwai scb->volume[1] = right;
2141da177e4SLinus Torvalds }
2151da177e4SLinus Torvalds #endif /* __DSP_SPOS_H__ */
2161da177e4SLinus Torvalds #endif /* CONFIG_SND_CS46XX_NEW_DSP */
217