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/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.h99 #define BWN_NTAB_TYPEMASK 0xF0000000
100 #define BWN_NTAB_8BIT 0x10000000
101 #define BWN_NTAB_16BIT 0x20000000
102 #define BWN_NTAB_32BIT 0x30000000
108 #define BWN_NTAB_FRAMESTRUCT BWN_NTAB32(0x0A, 0x000) /* Frame Struct Table */
110 #define BWN_NTAB_FRAMELT BWN_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
112 #define BWN_NTAB_TMAP BWN_NTAB32(0x0C, 0x000) /* T Map Table */
114 #define BWN_NTAB_TDTRN BWN_NTAB32(0x0E, 0x000) /* TDTRN Table */
116 #define BWN_NTAB_INTLEVEL BWN_NTAB32(0x0D, 0x000) /* Int Level Table */
118 #define BWN_NTAB_PILOT BWN_NTAB16(0x0B, 0x000) /* Pilot Table */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pinctrl.dtsi37 reg = <0x00140000 0x250>;
45 reg = <0x0014029c 0x26c>;
47 #size-cells = <0>;
49 pinctrl-single,function-mask = <0xf>;
51 &range 0 91 MODE_GPIO
61 0x038 MODE_NITRO /* tsio_0 */
62 0x03c MODE_NITRO /* tsio_1 */
68 0x0ac MODE_PNOR /* nand_ce1_n */
69 0x0b0 MODE_PNOR /* nand_ce0_n */
70 0x0b4 MODE_PNOR /* nand_we_n */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721s2-evm-gesi-exp-board.dtso27 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
28 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
34 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
35 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
36 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
37 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
38 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
39 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
40 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
41 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx.dts22 dcr-parent = <&{/cpus/cpu@0}>;
30 #size-cells = <0>;
32 cpu@0 {
35 reg = <0x00000000>;
49 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
67 dcr-reg = <0x0d0 0x009>;
[all …]
H A Dklondike.dts16 dcr-parent = <&{/cpus/cpu@0}>;
25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0x00000000>;
44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
50 cell-index = <0>;
51 dcr-reg = <0x0c0 0x010>;
52 #address-cells = <0>;
53 #size-cells = <0>;
61 dcr-reg = <0x0d0 0x010>;
[all …]
H A Dacadia.dts18 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
34 clock-frequency = <0>; /* Filled in by wrapper */
35 timebase-frequency = <0>; /* Filled in by wrapper */
47 reg = <0x0 0x0>; /* Filled in by wrapper */
53 dcr-reg = <0x0c0 0x009>;
54 cell-index = <0>;
55 #address-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey960-pinctrl.dtsi18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_gen4vf_hw_csr_data.h6 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0
7 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
8 #define ADF_RING_CSR_RING_HEAD 0x0C0
9 #define ADF_RING_CSR_RING_TAIL 0x100
10 #define ADF_RING_CSR_E_STAT 0x14C
11 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000
12 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040
13 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080
14 #define ADF_RING_CSR_INT_FLAG 0x170
15 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
[all …]
/freebsd/sys/powerpc/mpc85xx/
H A Dlbc.h36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
38 #define LBC85XX_MAR 0x068 /* UPM address register */
39 #define LBC85XX_MAMR 0x070 /* UPMA mode register */
40 #define LBC85XX_MBMR 0x074 /* UPMB mode register */
41 #define LBC85XX_MCMR 0x078 /* UPMC mode register */
42 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */
43 #define LBC85XX_MDR 0x088 /* UPM data register */
44 #define LBC85XX_LSOR 0x090 /* Special operation initiation */
45 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_soctherm.c55 /* Per sensors registers - base is 0x0c0*/
56 #define TSENSOR_CONFIG0 0x000
57 #define TSENSOR_CONFIG0_TALL(x) (((x) & 0xFFFFF) << 8)
63 #define TSENSOR_CONFIG0_STOP (1 << 0)
65 #define TSENSOR_CONFIG1 0x004
67 #define TSENSOR_CONFIG1_TEN_COUNT(x) (((x) & 0x3F) << 24)
68 #define TSENSOR_CONFIG1_TIDDQ_EN(x) (((x) & 0x3F) << 15)
69 #define TSENSOR_CONFIG1_TSAMPLE(x) (((x) & 0x3FF) << 0)
71 #define TSENSOR_CONFIG2 0x008
72 #define TSENSOR_CONFIG2_THERMA(x) (((x) & 0xFFFF) << 16)
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatopreg.h32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000
33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004
34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008
35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C
36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F
39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16)
40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010
41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dadf_transport_access_macros.h7 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
8 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
9 #define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF
10 #define ADF_RING_CSR_RING_CONFIG 0x000
11 #define ADF_RING_CSR_RING_LBASE 0x040
12 #define ADF_RING_CSR_RING_UBASE 0x080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
[all …]
H A Dadf_gen4_hw_data.h9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10 #define ADF_RING_CSR_RING_CONFIG 0x1000
11 #define ADF_RING_CSR_RING_LBASE 0x1040
12 #define ADF_RING_CSR_RING_UBASE 0x1080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_COL_CTL 0x180
[all …]
H A Dadf_gen2_hw_data.h10 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12 #define ADF_RING_CSR_RING_CONFIG 0x000
13 #define ADF_RING_CSR_RING_LBASE 0x040
14 #define ADF_RING_CSR_RING_UBASE 0x080
15 #define ADF_RING_CSR_RING_HEAD 0x0C0
16 #define ADF_RING_CSR_RING_TAIL 0x100
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_INT_FLAG 0x170
19 #define ADF_RING_CSR_INT_SRCSEL 0x174
[all …]
H A Dicp_qat_hal.h9 MISC_CONTROL = 0x04,
10 ICP_RESET = 0x0c,
11 ICP_GLOBAL_CLK_ENABLE = 0x50
14 enum { MISC_CONTROL_C4XXX = 0xAA0,
15 ICP_RESET_CPP0 = 0x938,
16 ICP_RESET_CPP1 = 0x93c,
17 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964,
18 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 };
21 USTORE_ADDRESS = 0x000,
22 USTORE_DATA_LOWER = 0x004,
[all …]
/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dwcs.h33 0x011, // 00000 = 0 - PHY_RESET_START
34 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY
35 0x009, // 0x002 = 2 -
36 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE
37 0x010, // 0x004 = 4 -
38 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED
39 0x01e, // 0x006 = 6 -
40 0x0ff, // 0x007 = 7 - JUMP
41 0x001, // 0x008 = 8 -
42 0x010, // 0x009 = 9 - SEND_ID_FRAME
[all …]
/freebsd/sys/dev/bhnd/nvram/
H A Dnvram_map36 help "Antennas 0-3 are marked as available if the
41 help "Antennas 0-3 are marked as available if the
46 desc "Antenna 0 Gain"
72 help "TX chains 0-3 are marked as available if the
80 help "RX chains 0-3 are marked as available if the
1863 0x048: u8 il0macaddr[6] { +0x1, +0x0, +0x3, +0x2, +0x5, +0x4 }
1864 0x04C: u16 boardnum
1865 0x054: u8 et1macaddr[6] { +0x1, +0x0, +0x3, +0x2, +0x5, +0x4 }
1866 0x05C: u8 boardrev
1867 0x05D: u8 aa5g (&0xC0, >>6)
[all …]

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