Lines Matching +full:0 +full:x0c0

18 	dcr-parent = <&{/cpus/cpu@0}>;
28 		#size-cells = <0>;
30 		cpu@0 {
33 			reg = <0x0>;
34 			clock-frequency = <0>; /* Filled in by wrapper */
35 			timebase-frequency = <0>; /* Filled in by wrapper */
47 		reg = <0x0 0x0>; /* Filled in by wrapper */
53 		dcr-reg = <0x0c0 0x009>;
54 		cell-index = <0>;
55 		#address-cells = <0>;
56 		#size-cells = <0>;
65 		clock-frequency = <0>; /* Filled in by wrapper */
69 			dcr-reg = <0x380 0x62>;
78 				0x13 0x4 /* TXEOB */
79 				0x15 0x4 /* RXEOB */
80 				0x12 0x4 /* SERR, TXDE, RXDE */>;
88 			dcr-reg = <0x0a 0x05>;
89 			clock-frequency = <0>; /* Filled in by wrapper */
94 				reg = <0xef600300 0x8>;
95 				virtual-reg = <0xef600300>;
96 				clock-frequency = <0>; /* Filled in by wrapper */
99 				interrupts = <0x5 0x4>;
105 				reg = <0xef600400 0x8>;
106 				clock-frequency = <0>; /* Filled in by wrapper */
109 				interrupts = <0x6 0x4>;
114 				reg = <0xef600500 0x11>;
116 				interrupts = <0xa 0x4>;
121 				reg = <0xef600700 0x20>;
126 				reg = <0xef600800 0x20>;
134 					0x10 0x4 /* Ethernet */
135 					0x11 0x4 /* Ethernet Wake up */>;
137 				reg = <0xef600900 0x70>;
139 				mal-tx-channel = <0>;
140 				mal-rx-channel = <0>;
141 				cell-index = <0>;
146 				phy-map = <0x0>;
151 				reg = <0xef601000 0x620>;
153 				interrupts = <0x7 0x4>;
158 				reg = <0xef601800 0x620>;
160 				interrupts = <0x8 0x4>;
165 				reg = <0xef602000 0x800>;
167 				interrupts = <0xb 0x4 0xc 0x4>;
172 				reg = <0xef602800 0x60>;
174 				interrupts = <0x4 0x4>;
180 				dcr-reg = <0xe0 0x9>;
185 				reg = <0xef603000 0x80>;
187 				interrupts = <0xd 0x4 0xe 0x4>;
192 				reg = <0xef603300 0x40>;
194 				interrupts = <0x18 0x4>;
199 				reg = <0xef603400 0x40>;
201 				interrupts = <0x17 0x4>;
206 				reg = <0xef603500 0x100>;
208 				interrupts = <0x9 0x4>;
214 			dcr-reg = <0x12 0x2>;
217 			clock-frequency = <0>; /* Filled in by wrapper */