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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
H A Dqcom,sm6150-mdss.yaml47 "^display-controller@[0-9a-f]+$":
54 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
84 reg = <0x0ae00000 0x1000>;
103 iommus = <&apps_smmu 0x800 0x0>;
109 reg = <0x0ae01000 0x8f000>,
110 <0x0aeb0000 0x2008>;
126 interrupts = <0>;
130 #size-cells = <0>;
132 port@0 {
[all …]
H A Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
99 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x820 0x402>;
124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
H A Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]
H A Dqcom,sm8550-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x1c00 0x2>;
120 reg = <0x0ae01000 0x8f000>,
121 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sc7180-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
99 reg = <0x0ae00000 0x1000>;
118 iommus = <&apps_smmu 0x820 0x402>;
126 reg = <0x0ae01000 0x8f000>,
127 <0x0aeb0000 0x2008>;
143 interrupts = <0>;
147 #size-cells = <0>;
[all …]
H A Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x800 0x420>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
140 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x2800 0x402>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
147 interrupts = <0>;
151 #size-cells = <0>;
[all …]
H A Dqcom,sc7280-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^edp@[0-9a-f]+$":
83 "^phy@[0-9a-f]+$":
111 reg = <0xae00000 0x1000>;
130 iommus = <&apps_smmu 0x900 0x402>;
135 reg = <0x0ae01000 0x8f000>,
136 <0x0aeb0000 0x2008>;
154 interrupts = <0>;
[all …]
H A Dqcom,sm7150-mdss.yaml52 "^display-controller@[0-9a-f]+$":
59 "^displayport-controller@[0-9a-f]+$":
66 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
97 reg = <0x0ae00000 0x1000>;
125 iommus = <&apps_smmu 0x800 0x440>;
133 reg = <0x0ae01000 0x8f000>,
134 <0x0aeb0000 0x2008>;
157 interrupts = <0>;
161 #size-cells = <0>;
[all …]
H A Ddsi-controller-main.yaml135 port@0:
149 enum: [ 0, 1, 2, 3 ]
165 enum: [ 0, 1, 2, 3 ]
184 - port@0
428 reg = <0x0ae94000 0x400>;
432 #size-cells = <0>;
454 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
461 #size-cells = <0>;
463 port@0 {
464 reg = <0>;
[all …]