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/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/arch/powerpc/include/asm/
H A Dio-workarounds.h30 #define SPIDER_PCI_REG_BASE 0xd000
31 #define SPIDER_PCI_REG_SIZE 0x1000
32 #define SPIDER_PCI_VCI_CNTL_STAT 0x0110
33 #define SPIDER_PCI_DUMMY_READ 0x0810
34 #define SPIDER_PCI_DUMMY_READ_BASE 0x0814
/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-d680-dmb.c12 { 0x0038, KEY_SWITCHVIDEOMODE }, /* TV/AV */
13 { 0x080c, KEY_ZOOM },
14 { 0x0800, KEY_NUMERIC_0 },
15 { 0x0001, KEY_NUMERIC_1 },
16 { 0x0802, KEY_NUMERIC_2 },
17 { 0x0003, KEY_NUMERIC_3 },
18 { 0x0804, KEY_NUMERIC_4 },
19 { 0x0005, KEY_NUMERIC_5 },
20 { 0x0806, KEY_NUMERIC_6 },
21 { 0x0007, KEY_NUMERIC_7 },
[all …]
H A Drc-anysee.c12 { 0x0800, KEY_NUMERIC_0 },
13 { 0x0801, KEY_NUMERIC_1 },
14 { 0x0802, KEY_NUMERIC_2 },
15 { 0x0803, KEY_NUMERIC_3 },
16 { 0x0804, KEY_NUMERIC_4 },
17 { 0x0805, KEY_NUMERIC_5 },
18 { 0x0806, KEY_NUMERIC_6 },
19 { 0x0807, KEY_NUMERIC_7 },
20 { 0x0808, KEY_NUMERIC_8 },
21 { 0x0809, KEY_NUMERIC_9 },
[all …]
H A Drc-asus-ps3-100.c12 { 0x081c, KEY_HOME }, /* home */
13 { 0x081e, KEY_TV }, /* tv */
14 { 0x0803, KEY_TEXT }, /* teletext */
15 { 0x0829, KEY_POWER }, /* close */
17 { 0x080b, KEY_RED }, /* red */
18 { 0x080d, KEY_YELLOW }, /* yellow */
19 { 0x0806, KEY_BLUE }, /* blue */
20 { 0x0807, KEY_GREEN }, /* green */
22 /* Keys 0 to 9 */
23 { 0x082a, KEY_NUMERIC_0 },
[all …]
H A Drc-asus-pc39.c18 /* Keys 0 to 9 */
19 { 0x082a, KEY_NUMERIC_0 },
20 { 0x0816, KEY_NUMERIC_1 },
21 { 0x0812, KEY_NUMERIC_2 },
22 { 0x0814, KEY_NUMERIC_3 },
23 { 0x0836, KEY_NUMERIC_4 },
24 { 0x0832, KEY_NUMERIC_5 },
25 { 0x0834, KEY_NUMERIC_6 },
26 { 0x080e, KEY_NUMERIC_7 },
27 { 0x080a, KEY_NUMERIC_8 },
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
H A Dgt200.c33 .mthd = 0x0000,
34 .addr = 0x000000,
36 { 0x0080, 0x000000 },
37 { 0x0084, 0x6109a0 },
38 { 0x0088, 0x6109c0 },
39 { 0x008c, 0x6109c8 },
40 { 0x0090, 0x6109b4 },
41 { 0x0094, 0x610970 },
42 { 0x00a0, 0x610998 },
43 { 0x00a4, 0x610964 },
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx1.c17 #define MX1_CCM_BASE_ADDR 0x0021b000
18 #define MX1_TIM1_BASE_ADDR 0x00220000
29 #define CCM_CSCR (ccm + 0x0000)
30 #define CCM_MPCTL0 (ccm + 0x0004)
31 #define CCM_SPCTL0 (ccm + 0x000c)
32 #define CCM_PCDR (ccm + 0x0020)
33 #define SCM_GCCR (ccm + 0x0810)
37 ccm = of_iomap(np, 0); in mx1_clocks_init_dt()
40 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx1_clocks_init_dt()
47 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in mx1_clocks_init_dt()
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_cldma.h25 #define CLDMA_ALL_Q GENMASK(7, 0)
29 #define TXRX_STATUS_BITMASK GENMASK(7, 0)
40 #define CLDMA0_AO_BASE 0x10049000
41 #define CLDMA0_PD_BASE 0x1021d000
42 #define CLDMA1_AO_BASE 0x1004b000
43 #define CLDMA1_PD_BASE 0x1021f000
45 #define CLDMA_R_AO_BASE 0x10023000
46 #define CLDMA_R_PD_BASE 0x1023d000
49 #define REG_CLDMA_UL_START_ADDRL_0 0x0004
50 #define REG_CLDMA_UL_START_ADDRH_0 0x0008
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm8148-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
H A Ddra62x-j5eco-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
/linux/drivers/net/ethernet/engleder/
H A Dtsnep_hw.h12 #define ECM_TYPE 0x0000
13 #define ECM_REVISION_MASK 0x000000FF
14 #define ECM_REVISION_SHIFT 0
15 #define ECM_VERSION_MASK 0x0000FF00
17 #define ECM_QUEUE_COUNT_MASK 0x00070000
19 #define ECM_GATE_CONTROL 0x02000000
22 #define ECM_SYSTEM_TIME_LOW 0x0008
23 #define ECM_SYSTEM_TIME_HIGH 0x000C
26 #define ECM_CLOCK_RATE 0x0010
27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
67 cr11 |= 0x80; in NVLockUnlock()
69 cr11 &= ~0x80; in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
78 (ShowHide & 0x01); in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h25 // base address: 0x8000
26 …GRBM_CNTL 0x0000
27 …ne mmGRBM_CNTL_BASE_IDX 0
28 …GRBM_SKEW_CNTL 0x0001
29 …ne mmGRBM_SKEW_CNTL_BASE_IDX 0
30 …GRBM_STATUS2 0x0002
31 …ne mmGRBM_STATUS2_BASE_IDX 0
32 …GRBM_PWR_CNTL 0x0003
33 …ne mmGRBM_PWR_CNTL_BASE_IDX 0
34 …GRBM_STATUS 0x0004
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h19 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
20 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
21 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
22 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
23 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
24 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
25 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
26 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
27 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
28 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
[all …]
/linux/include/video/
H A Datmel_lcdc.h18 #define ATMEL_LCDC_WIRING_BGR 0
37 #define ATMEL_LCDC_DMABADDR1 0x00
38 #define ATMEL_LCDC_DMABADDR2 0x04
39 #define ATMEL_LCDC_DMAFRMPT1 0x08
40 #define ATMEL_LCDC_DMAFRMPT2 0x0c
41 #define ATMEL_LCDC_DMAFRMADD1 0x10
42 #define ATMEL_LCDC_DMAFRMADD2 0x14
44 #define ATMEL_LCDC_DMAFRMCFG 0x18
45 #define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
47 #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
[all …]
/linux/arch/powerpc/platforms/ps3/
H A Dspu.c36 SPE_TYPE_LOGICAL = 0,
46 u8 padding_0140[0x0140];
47 u64 int_status_class0_RW; /* 0x0140 */
48 u64 int_status_class1_RW; /* 0x0148 */
49 u64 int_status_class2_RW; /* 0x0150 */
50 u8 padding_0158[0x0610-0x0158];
51 u64 mfc_dsisr_RW; /* 0x0610 */
52 u8 padding_0618[0x0620-0x0618];
53 u64 mfc_dar_RW; /* 0x0620 */
54 u8 padding_0628[0x0800-0x0628];
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm845-camss.yaml96 port@0:
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
[all …]
/linux/drivers/media/usb/gspca/
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
[all …]
H A Dcl902d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
38 …_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
[all …]
/linux/drivers/hwtracing/ptt/
H A Dhisi_ptt.h30 #define HISI_PTT_TUNING_CTRL 0x0000
31 #define HISI_PTT_TUNING_CTRL_CODE GENMASK(15, 0)
33 #define HISI_PTT_TUNING_DATA 0x0004
34 #define HISI_PTT_TUNING_DATA_VAL_MASK GENMASK(15, 0)
35 #define HISI_PTT_TRACE_ADDR_SIZE 0x0800
36 #define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810
37 #define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814
38 #define HISI_PTT_TRACE_ADDR_STRIDE 0x8
39 #define HISI_PTT_TRACE_CTRL 0x0850
40 #define HISI_PTT_TRACE_CTRL_EN BIT(0)
[all …]

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