Lines Matching +full:0 +full:x0810

25 #define CLDMA_ALL_Q			GENMASK(7, 0)
29 #define TXRX_STATUS_BITMASK		GENMASK(7, 0)
40 #define CLDMA0_AO_BASE			0x10049000
41 #define CLDMA0_PD_BASE			0x1021d000
42 #define CLDMA1_AO_BASE			0x1004b000
43 #define CLDMA1_PD_BASE			0x1021f000
45 #define CLDMA_R_AO_BASE			0x10023000
46 #define CLDMA_R_PD_BASE			0x1023d000
49 #define REG_CLDMA_UL_START_ADDRL_0	0x0004
50 #define REG_CLDMA_UL_START_ADDRH_0	0x0008
51 #define REG_CLDMA_UL_CURRENT_ADDRL_0	0x0044
52 #define REG_CLDMA_UL_CURRENT_ADDRH_0	0x0048
53 #define REG_CLDMA_UL_STATUS		0x0084
54 #define REG_CLDMA_UL_START_CMD		0x0088
55 #define REG_CLDMA_UL_RESUME_CMD		0x008c
56 #define REG_CLDMA_UL_STOP_CMD		0x0090
57 #define REG_CLDMA_UL_ERROR		0x0094
58 #define REG_CLDMA_UL_CFG		0x0098
64 #define REG_CLDMA_UL_MEM		0x009c
65 #define UL_MEM_CHECK_DIS		BIT(0)
68 #define REG_CLDMA_DL_START_CMD		0x05bc
69 #define REG_CLDMA_DL_RESUME_CMD		0x05c0
70 #define REG_CLDMA_DL_STOP_CMD		0x05c4
71 #define REG_CLDMA_DL_MEM		0x0508
72 #define DL_MEM_CHECK_DIS		BIT(0)
74 #define REG_CLDMA_DL_CFG		0x0404
81 #define REG_CLDMA_DL_START_ADDRL_0	0x0478
82 #define REG_CLDMA_DL_START_ADDRH_0	0x047c
83 #define REG_CLDMA_DL_CURRENT_ADDRL_0	0x04b8
84 #define REG_CLDMA_DL_CURRENT_ADDRH_0	0x04bc
85 #define REG_CLDMA_DL_STATUS		0x04f8
88 #define REG_CLDMA_L2TISAR0		0x0810
89 #define REG_CLDMA_L2TISAR1		0x0814
90 #define REG_CLDMA_L2TIMR0		0x0818
91 #define REG_CLDMA_L2TIMR1		0x081c
92 #define REG_CLDMA_L2TIMCR0		0x0820
93 #define REG_CLDMA_L2TIMCR1		0x0824
94 #define REG_CLDMA_L2TIMSR0		0x0828
95 #define REG_CLDMA_L2TIMSR1		0x082c
96 #define REG_CLDMA_L3TISAR0		0x0830
97 #define REG_CLDMA_L3TISAR1		0x0834
98 #define REG_CLDMA_L2RISAR0		0x0850
99 #define REG_CLDMA_L2RISAR1		0x0854
100 #define REG_CLDMA_L3RISAR0		0x0870
101 #define REG_CLDMA_L3RISAR1		0x0874
102 #define REG_CLDMA_IP_BUSY		0x08b4
103 #define IP_BUSY_WAKEUP			BIT(0)
104 #define CLDMA_L2TISAR0_ALL_INT_MASK	GENMASK(15, 0)
105 #define CLDMA_L2RISAR0_ALL_INT_MASK	GENMASK(15, 0)
108 #define REG_CLDMA_L2RIMR0		0x0858
109 #define REG_CLDMA_L2RIMR1		0x085c
110 #define REG_CLDMA_L2RIMCR0		0x0860
111 #define REG_CLDMA_L2RIMCR1		0x0864
112 #define REG_CLDMA_L2RIMSR0		0x0868
113 #define REG_CLDMA_L2RIMSR1		0x086c
114 #define REG_CLDMA_BUSY_MASK		0x0954
115 #define BUSY_MASK_PCIE			BIT(0)
119 #define REG_CLDMA_INT_MASK		0x0960
122 #define REG_INFRA_RST4_SET		0x0730
125 #define REG_INFRA_RST4_CLR		0x0734
128 #define REG_INFRA_RST2_SET		0x0140
131 #define REG_INFRA_RST2_CLR		0x0144