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/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dmcu.h12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwlf,wm8904.yaml27 const: 0
59 If any entry has the value 0xFFFF, the related register won't be set.
60 default: [0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF]
68 default: [0, 0]
137 #size-cells = <0>;
141 reg = <0x1a>;
154 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
156 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
160 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
161 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dgnu15 0 string \336\22\4\225 GNU message catalog (little endian),
16 #0 ulelong 0x950412DE GNU-format message catalog data
18 #>0 use gettext-object
19 #0 name gettext-object
27 >4 ulelong/0xFFff x %u.
29 >4 ulelong&0x0000FFff x \b%u
37 # for revision x.0 offset of table with originals is 1Ch if directly after header
38 >4 ulelong&0x0000FFff =0
39 >>12 ulelong !0x1C \b, at %#x string table
41 >4 ulelong&0x0000FFff >0
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/sys/dev/sound/usb/
H A Duaudioreg.h38 #define UAUDIO_VERSION_10 0x0100
39 #define UAUDIO_VERSION_20 0x0200
40 #define UAUDIO_VERSION_30 0x0300
42 #define UAUDIO_PROTOCOL_20 0x20
44 #define UDESC_CS_UNDEFINED 0x20
45 #define UDESC_CS_DEVICE 0x21
46 #define UDESC_CS_CONFIG 0x22
47 #define UDESC_CS_STRING 0x23
48 #define UDESC_CS_INTERFACE 0x24
49 #define UDESC_CS_ENDPOINT 0x25
[all …]
/freebsd/sys/dev/iwi/
H A Dif_iwireg.h38 #define IWI_CSR_INTR 0x0008
39 #define IWI_CSR_INTR_MASK 0x000c
40 #define IWI_CSR_INDIRECT_ADDR 0x0010
41 #define IWI_CSR_INDIRECT_DATA 0x0014
42 #define IWI_CSR_AUTOINC_ADDR 0x0018
43 #define IWI_CSR_AUTOINC_DATA 0x001c
44 #define IWI_CSR_RST 0x0020
45 #define IWI_CSR_CTL 0x0024
46 #define IWI_CSR_IO 0x0030
47 #define IWI_CSR_CMD_BASE 0x0200
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]
/freebsd/sys/dev/ftgpio/
H A Dftgpio.c57 #define GPIO4_ENABLE 0x28
58 #define GPIO3_ENABLE 0x29
59 #define FULL_UR5_UR6 0x2A
60 #define GPIO1_ENABLE 0x2B
61 #define GPIO2_ENABLE 0x2C
64 #define FTGPIO_LDN_GPIO 0x06
69 #define FTGPIO_IS_VALID_PIN(_p) ((_p) >= 0 && (_p) <= FTGPIO_MAX_PIN)
82 } while (0)
89 #define REG_OUTPUT_ENABLE 0 /* Not for GPIO0 */
105 .devid = 0x0704,
[all …]
/freebsd/sys/dev/ixl/
H A Di40e_adminq_cmd.h44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
46 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
53 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
55 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
57 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
59 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
86 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
91 #define I40E_AQ_FLAG_DD_SHIFT 0
103 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852bt_rfk.c17 #define RTW8852BT_RXDCK_VER 0x1
18 #define RTW8852BT_IQK_VER 0x2a
21 #define RTW8852BT_DPK_VER 0x06
25 #define DPK_TXAGC_LOWER 0x2e
26 #define DPK_TXAGC_UPPER 0x3f
27 #define DPK_TXAGC_INVAL 0xff
28 #define RFREG_MASKRXBB 0x003e0
29 #define RFREG_MASKMODE 0xf0000
32 RF_SHUT_DOWN = 0x0,
33 RF_STANDBY = 0x1,
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_type_e610.h77 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
80 (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
83 #define HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
84 #define LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
85 #define HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
86 #define LO_WORD(x) ((u16)((x) & 0xFFFF))
87 #define HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
88 #define LO_BYTE(x) ((u8)((x) & 0xFF))
94 #define IS_ASCII(_ch) ((_ch) < 0x80)
113 #define E610_SR_NVM_DEV_STARTER_VER 0x18
[all …]
/freebsd/sys/dev/superio/
H A Dsuperio.c110 bus_write_1(res, 0, reg); in sio_read()
129 bus_write_1(res, 0, reg); in sio_write()
170 printf("ignored attempt to write special register 0x%x\n", reg); in sio_ldn_write()
189 sc->current_ldn = 0xff; in sio_conf_exit()
196 bus_write_1(res, 0, 0x87); in ite_conf_enter()
197 bus_write_1(res, 0, 0x01); in ite_conf_enter()
198 bus_write_1(res, 0, 0x55); in ite_conf_enter()
199 bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa); in ite_conf_enter()
205 sio_write(res, 0x02, 0x02); in ite_conf_exit()
217 bus_write_1(res, 0, 0x87); in nvt_conf_enter()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx94-pinfunc.h10 #define IMX94_DSE_X1 0x2
11 #define IMX94_DSE_X2 0x6
12 #define IMX94_DSE_X3 0xe
13 #define IMX94_DSE_X4 0x1e
14 #define IMX94_DSE_X5 0x3e
15 #define IMX94_DSE_X6 0x7e
18 #define IMX94_FSEL_FAST 0x180
19 #define IMX94_FSEL_SLOW 0x100
22 #define IMX94_PU_ENABLE 0x200
23 #define IMX94_PU_DISABLE 0x0
[all …]
/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
59 /* Get version (direct 0x0001) */
73 /* Send driver version (indirect 0x0002) */
84 /* Queue Shutdown (direct 0x0003) */
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
91 /* Get Expanded Error Code (0x0005, direct) */
94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF
99 /* Request resource ownership (direct 0x0008)
100 * Release resource ownership (direct 0x0009)
125 #define ICE_AQ_RES_GLBL_SUCCESS 0
[all...]
H A Dice_nvm.c34 #define GL_MNG_DEF_DEVID 0x000B611C
47 * Read the NVM using the admin queue commands (0x0701)
73 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF); in ice_aq_read_nvm()
74 cmd->offset_high = (offset >> 16) & 0xFF; in ice_aq_read_nvm()
100 u32 bytes_read = 0; in ice_read_flat_nvm()
106 *length = 0; in ice_read_flat_nvm()
158 * Update the NVM using the admin queue commands (0x0703)
173 if (offset & 0xFF000000) in ice_aq_update_nvm()
184 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF); in ice_aq_update_nvm()
185 cmd->offset_high = (offset >> 16) & 0xF in ice_aq_update_nvm()
[all...]
/freebsd/sys/dev/bwn/
H A Dif_bwnreg.h36 #define BWN_IOCTL_PHYCLOCK_ENABLE 0x0004
37 #define BWN_IOCTL_PHYRESET 0x0008
38 #define BWN_IOCTL_MACPHYCLKEN 0x0010 /* MAC PHY Clock Control Enable (rev >= 5) */
39 #define BWN_IOCTL_PLLREFSEL 0x0020 /* PLL Frequency Reference Select (rev >= 5) */
41 #define BWN_IOCTL_PHY_BANDWIDTH 0x00C0
42 #define BWN_IOCTL_PHY_BANDWIDTH_10MHZ 0x0000
43 #define BWN_IOCTL_PHY_BANDWIDTH_20MHZ 0x0040
44 #define BWN_IOCTL_PHY_BANDWIDTH_40MHZ 0x0080
45 #define BWN_IOCTL_SUPPORT_G 0x2000
48 #define BWN_IOST_HAVE_2GHZ 0x0001
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/fb/
H A Dvga.c37 #define FB_DEBUG 0
65 #define VGA_DEBUG 0
82 return 0; in vga_probe_unit()
87 return 0; in vga_probe_unit()
136 #define RTC_EQUIPMENT 0x14
145 #define V_STATE_SIG 0x736f6962
151 #define DCC_MONO 0
165 { 0, KD_MONO, "mda", 0, 0, 0, IO_MDA, IO_MDASIZE, MONO_CRTC,
167 0, 0, 0, 0, 7, 0, },
169 { 0, KD_CGA, "cga", 0, 0, V_ADP_COLOR, IO_CGA, IO_CGASIZE, COLOR_CRTC,
[all …]

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