1*6c92544dSBjoern A. Zeeb /* SPDX-License-Identifier: ISC */ 2*6c92544dSBjoern A. Zeeb /* 3*6c92544dSBjoern A. Zeeb * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4*6c92544dSBjoern A. Zeeb */ 5*6c92544dSBjoern A. Zeeb 6*6c92544dSBjoern A. Zeeb #ifndef __MT76x2_MCU_H 7*6c92544dSBjoern A. Zeeb #define __MT76x2_MCU_H 8*6c92544dSBjoern A. Zeeb 9*6c92544dSBjoern A. Zeeb #include "../mt76x02_mcu.h" 10*6c92544dSBjoern A. Zeeb 11*6c92544dSBjoern A. Zeeb /* Register definitions */ 12*6c92544dSBjoern A. Zeeb #define MT_MCU_CPU_CTL 0x0704 13*6c92544dSBjoern A. Zeeb #define MT_MCU_CLOCK_CTL 0x0708 14*6c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_BASE1 0x0740 15*6c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_BASE2 0x0744 16*6c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_BASE3 0x0748 17*6c92544dSBjoern A. Zeeb 18*6c92544dSBjoern A. Zeeb #define MT_MCU_ROM_PATCH_OFFSET 0x80000 19*6c92544dSBjoern A. Zeeb #define MT_MCU_ROM_PATCH_ADDR 0x90000 20*6c92544dSBjoern A. Zeeb 21*6c92544dSBjoern A. Zeeb #define MT_MCU_ILM_OFFSET 0x80000 22*6c92544dSBjoern A. Zeeb 23*6c92544dSBjoern A. Zeeb #define MT_MCU_DLM_OFFSET 0x100000 24*6c92544dSBjoern A. Zeeb #define MT_MCU_DLM_ADDR 0x90000 25*6c92544dSBjoern A. Zeeb #define MT_MCU_DLM_ADDR_E3 0x90800 26*6c92544dSBjoern A. Zeeb 27*6c92544dSBjoern A. Zeeb enum mcu_calibration { 28*6c92544dSBjoern A. Zeeb MCU_CAL_R = 1, 29*6c92544dSBjoern A. Zeeb MCU_CAL_TEMP_SENSOR, 30*6c92544dSBjoern A. Zeeb MCU_CAL_RXDCOC, 31*6c92544dSBjoern A. Zeeb MCU_CAL_RC, 32*6c92544dSBjoern A. Zeeb MCU_CAL_SX_LOGEN, 33*6c92544dSBjoern A. Zeeb MCU_CAL_LC, 34*6c92544dSBjoern A. Zeeb MCU_CAL_TX_LOFT, 35*6c92544dSBjoern A. Zeeb MCU_CAL_TXIQ, 36*6c92544dSBjoern A. Zeeb MCU_CAL_TSSI, 37*6c92544dSBjoern A. Zeeb MCU_CAL_TSSI_COMP, 38*6c92544dSBjoern A. Zeeb MCU_CAL_DPD, 39*6c92544dSBjoern A. Zeeb MCU_CAL_RXIQC_FI, 40*6c92544dSBjoern A. Zeeb MCU_CAL_RXIQC_FD, 41*6c92544dSBjoern A. Zeeb MCU_CAL_PWRON, 42*6c92544dSBjoern A. Zeeb MCU_CAL_TX_SHAPING, 43*6c92544dSBjoern A. Zeeb }; 44*6c92544dSBjoern A. Zeeb 45*6c92544dSBjoern A. Zeeb enum mt76x2_mcu_cr_mode { 46*6c92544dSBjoern A. Zeeb MT_RF_CR, 47*6c92544dSBjoern A. Zeeb MT_BBP_CR, 48*6c92544dSBjoern A. Zeeb MT_RF_BBP_CR, 49*6c92544dSBjoern A. Zeeb MT_HL_TEMP_CR_UPDATE, 50*6c92544dSBjoern A. Zeeb }; 51*6c92544dSBjoern A. Zeeb 52*6c92544dSBjoern A. Zeeb struct mt76x2_tssi_comp { 53*6c92544dSBjoern A. Zeeb u8 pa_mode; 54*6c92544dSBjoern A. Zeeb u8 cal_mode; 55*6c92544dSBjoern A. Zeeb u16 pad; 56*6c92544dSBjoern A. Zeeb 57*6c92544dSBjoern A. Zeeb u8 slope0; 58*6c92544dSBjoern A. Zeeb u8 slope1; 59*6c92544dSBjoern A. Zeeb u8 offset0; 60*6c92544dSBjoern A. Zeeb u8 offset1; 61*6c92544dSBjoern A. Zeeb } __packed __aligned(4); 62*6c92544dSBjoern A. Zeeb 63*6c92544dSBjoern A. Zeeb int mt76x2_mcu_tssi_comp(struct mt76x02_dev *dev, 64*6c92544dSBjoern A. Zeeb struct mt76x2_tssi_comp *tssi_data); 65*6c92544dSBjoern A. Zeeb int mt76x2_mcu_init_gain(struct mt76x02_dev *dev, u8 channel, u32 gain, 66*6c92544dSBjoern A. Zeeb bool force); 67*6c92544dSBjoern A. Zeeb 68*6c92544dSBjoern A. Zeeb #endif 69