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/freebsd/sys/arm/arm/
H A Dcpu_asm-v6.S51 ands r0, r0, #0x07000000
67 ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
79 beq 3f /* at 0 means we are done */
87 teq r0, #0
91 mov r0, #0
100 ands r0, r0, #0x38000000
116 ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
128 beq 3f /* at 0 means we are done */
136 teq r0, #0
140 mov r0, #0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-db8500.dtsi8 operating-points = <998400 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
H A Dste-db8520.dtsi8 operating-points = <1152000 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
/freebsd/sys/contrib/device-tree/src/arm/nuvoton/
H A Dnuvoton-wpcm450-supermicro-x9sci-ln4f.dts7 /memreserve/ 0x07000000 0x01000000;
27 memory@0 {
29 reg = <0 0x08000000>; /* 128 MiB */
35 pinctrl-0 = <&key_pins>;
47 pinctrl-0 = <&led_pins>;
64 flash@0 {
65 reg = <0>;
72 /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "",
78 /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid",
84 /* 0 */ "", "", "", "", "", "", "", "",
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
H A Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nand@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k1000-ref.dts24 reg = <0x0 0x00200000 0x0 0x06e00000>,
25 <0x0 0x08000000 0x0 0x07000000>,
26 <0x0 0x90000000 0x1 0xe0000000>;
37 size = <0x0 0x2000000>;
51 #size-cells = <0>;
52 phy0: ethernet-phy@0 {
53 reg = <0>;
66 #size-cells = <0>;
76 pinctrl-0 = <&i2c0_pins_default>;
80 #size-cells = <0>;
[all …]
/freebsd/sys/dev/bhnd/
H A Dbhndreg.h32 #define BHND_DEFAULT_CHIPC_ADDR 0x18000000
38 #define BHND_DEFAULT_CORE_SIZE 0x1000
43 #define BHND_DEFAULT_ENUM_SIZE 0x00100000
56 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
57 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
58 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
59 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
60 #define BHND_CCS_FORCE_MASK 0x0000000F
62 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
63 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_s2m.h59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
63 /* [0x8] Descriptor read master configuration */
65 /* [0xc] Descriptor read master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Completion descriptors write master configuration */
77 /* [0x24] AXI outstanding read configuration */
[all …]
H A Dal_hal_udma_regs_m2s.h59 /* [0x0] Completion write master configuration */
61 /* [0x4] Completion write master configuration */
63 /* [0x8] Data read master configuration */
65 /* [0xc] Data read master configuration */
67 /* [0x10] Descriptor read master configuration */
69 /* [0x14] Descriptor read master configuration */
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Descriptors write master configuration (completion) */
77 /* [0x24] AXI outstanding configuration */
[all …]
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_hashfilter.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00010008/0x00010008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
[all …]
H A Dt5fw_cfg_hashfilter.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
H A Dt5fw_cfg.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
H A Dt6fw_cfg.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00012008/0x00012008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h24 #define AR_BT_COEX_MODE 0x8170
25 #define AR_BT_TIME_EXTEND 0x000000ff
26 #define AR_BT_TIME_EXTEND_S 0
27 #define AR_BT_TXSTATE_EXTEND 0x00000100
29 #define AR_BT_TX_FRAME_EXTEND 0x00000200
31 #define AR_BT_MODE 0x00000c00
33 #define AR_BT_QUIET 0x00001000
35 #define AR_BT_QCU_THRESH 0x0001e000
37 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
39 #define AR_BT_PRIORITY_TIME 0x00fc0000
[all …]
/freebsd/sys/dev/ath/ath_hal/
H A Dah_btcoex.h26 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
44 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
60 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
71 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
72 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
74 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
76 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
78 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
80 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
81 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0c>;
92 reg = <0x10060000 0x100>;
[all …]
/freebsd/sys/dev/ae/
H A Dif_aereg.h31 #define AE_MASTER_REG 0x1400
33 #define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
34 #define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
35 #define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
36 #define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
38 #define AE_MASTER_REVNUM_MASK 0xff
40 #define AE_MASTER_DEVID_MASK 0xff
45 #define AE_ISR_REG 0x1600
46 #define AE_ISR_TIMER 0x00000001 /* Counter expired. */
47 #define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
[all …]
/freebsd/sys/dev/mpi3mr/mpi/
H A Dmpi30_init.h53 U8 CDB[20]; /* 0x00 */
54 U32 PrimaryReferenceTag; /* 0x14 */
55 U16 PrimaryApplicationTag; /* 0x18 */
56 U16 PrimaryApplicationTagMask; /* 0x1A */
57 U32 TransferLength; /* 0x1C */
71 U16 HostTag; /* 0x00 */
72 U8 IOCUseOnly02; /* 0x02 */
73 U8 Function; /* 0x03 */
74 U16 IOCUseOnly04; /* 0x04 */
75 U8 IOCUseOnly06; /* 0x06 */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]

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