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/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmediatek,mt7621-pci-phy.yaml38 reg = <0x1e149000 0x0700>;
39 clocks = <&sysc 0>;
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_rx_desc.h34 #define R12A_RXDW1_AMSDU 0x00002000
35 #define R12A_RXDW1_AMPDU 0x00008000
36 #define R12A_RXDW1_CKSUM_ERR 0x00100000
37 #define R12A_RXDW1_IPV6 0x00200000
38 #define R12A_RXDW1_UDP 0x00400000
39 #define R12A_RXDW1_CKSUM 0x00800000
41 #define R12A_RXDW2_RPT_C2H 0x10000000
43 #define R12A_RXDW3_RATE_M 0x0000007f
44 #define R12A_RXDW3_RATE_S 0
46 #define R12A_RXDW4_SPLCP 0x00000001
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
H A Dip1000phy.c77 DRIVER_MODULE(ip1000phy, miibus, ip1000phy_driver, 0, 0);
113 (miibus_get_flags(dev) & MIIF_MACPRIV0) != 0) in ip1000phy_attach()
116 return (0); in ip1000phy_attach()
156 if ((ife->ifm_media & IFM_FDX) != 0) { in ip1000phy_service()
165 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) in ip1000phy_service()
168 gig = 0; in ip1000phy_service()
180 sc->mii_ticks = 0; in ip1000phy_service()
189 sc->mii_ticks = 0; in ip1000phy_service()
194 if (sc->mii_ticks++ == 0) in ip1000phy_service()
203 sc->mii_ticks = 0; in ip1000phy_service()
[all …]
H A De1000phyreg.h72 #define E1000_MAX_REG_ADDRESS 0x1F
74 #define E1000_CR 0x00 /* control register */
75 #define E1000_CR_SPEED_SELECT_MSB 0x0040
76 #define E1000_CR_COLL_TEST_ENABLE 0x0080
77 #define E1000_CR_FULL_DUPLEX 0x0100
78 #define E1000_CR_RESTART_AUTO_NEG 0x0200
79 #define E1000_CR_ISOLATE 0x0400
80 #define E1000_CR_POWER_DOWN 0x0800
81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
82 #define E1000_CR_SPEED_SELECT_LSB 0x2000
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7621.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0>;
33 #address-cells = <0>;
149 reg = <0x1e000000 0x100000>;
150 ranges = <0x0 0x1e000000 0x0fffff>;
155 sysc: syscon@0 {
157 reg = <0x0 0x100>;
171 reg = <0x100 0x100>;
177 reg = <0x600 0x100>;
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dmac.h32 #define WMI_HOST_RC_DS_FLAG 0x01
33 #define WMI_HOST_RC_CW40_FLAG 0x02
34 #define WMI_HOST_RC_SGI_FLAG 0x04
35 #define WMI_HOST_RC_HT_FLAG 0x08
36 #define WMI_HOST_RC_RTSCTS_FLAG 0x10
37 #define WMI_HOST_RC_TX_STBC_FLAG 0x20
38 #define WMI_HOST_RC_RX_STBC_FLAG 0xC0
40 #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100
41 #define WMI_HOST_RC_TS_FLAG 0x200
42 #define WMI_HOST_RC_UAPSD_FLAG 0x400
[all …]
/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_chan.c64 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0); in r21a_bypass_ext_lna_2ghz()
65 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0); in r21a_bypass_ext_lna_2ghz()
66 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07); in r21a_bypass_ext_lna_2ghz()
67 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700); in r21a_bypass_ext_lna_2ghz()
77 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); in r21a_set_band_2ghz()
80 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
81 R12A_RFE_PINMUX_LNA_MASK, 0x7000); in r21a_set_band_2ghz()
82 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
83 R12A_RFE_PINMUX_PA_A_MASK, 0x70); in r21a_set_band_2ghz()
87 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000); in r21a_set_band_2ghz()
[all …]
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/freebsd/sys/x86/include/
H A Dapm_bios.h25 #define APM_BIOS 0x53
26 #define APM_INT 0x15
29 #define APM_16BIT_SUPPORT 0x01
30 #define APM_32BIT_SUPPORT 0x02
31 #define APM_CPUIDLE_SLOW 0x04
32 #define APM_DISABLED 0x08
33 #define APM_DISENGAGED 0x10
36 #define APM_OURADDR 0x00080000
39 #define APM_INSTCHECK 0x00
40 #define APM_REALCONNECT 0x01
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/sys/ufs/ufs/
H A Dquota.h58 #define USRQUOTA 0 /* element used for user quotas */
77 #define SUBCMDMASK 0x00ff
81 #define Q_QUOTAON 0x0100 /* enable quotas */
82 #define Q_QUOTAOFF 0x0200 /* disable quotas */
83 #define Q_GETQUOTA32 0x0300 /* get limits and usage (32-bit version) */
84 #define Q_SETQUOTA32 0x0400 /* set limits and usage (32-bit version) */
85 #define Q_SETUSE32 0x0500 /* set usage (32-bit version) */
86 #define Q_SYNC 0x0600 /* sync disk copy of a filesystems quotas */
87 #define Q_GETQUOTA 0x0700 /* get limits and usage (64-bit version) */
88 #define Q_SETQUOTA 0x0800 /* set limits and usage (64-bit version) */
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.h43 #define ZY7_SCLR_SCL 0x0000
44 #define ZY7_SLCR_LOCK 0x0004
45 #define ZY7_SLCR_LOCK_MAGIC 0x767b
46 #define ZY7_SLCR_UNLOCK 0x0008
47 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
48 #define ZY7_SLCR_LOCKSTA 0x000c
51 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
52 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
53 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
54 #define ZY7_SLCR_PLL_CTRL_RESET (1 << 0)
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-gre.c46 #define GRE_CP 0x8000 /* checksum present */
47 #define GRE_RP 0x4000 /* routing present */
48 #define GRE_KP 0x2000 /* key present */
49 #define GRE_SP 0x1000 /* sequence# present */
50 #define GRE_sP 0x0800 /* source routing */
51 #define GRE_AP 0x0080 /* acknowledgment# present */
60 { 0, NULL }
63 #define GRE_RECRS_MASK 0x0700 /* recursion count */
64 #define GRE_VERS_MASK 0x0007 /* protocol version */
67 #define GRESRE_IP 0x0800 /* IP */
[all …]
/freebsd/sys/dev/ic/
H A Di82586.h64 #define IE_SCP_ADDR 0xfffff4
93 #define IE_RU_COMMAND 0x0070 /* mask for RU command */
94 #define IE_RU_NOP 0 /* for completeness */
95 #define IE_RU_START 0x0010 /* start receive unit command */
96 #define IE_RU_ENABLE 0x0020 /* enable receiver command */
97 #define IE_RU_DISABLE 0x0030 /* disable receiver command */
98 #define IE_RU_ABORT 0x0040 /* abort current receive operation */
100 #define IE_CU_COMMAND 0x0700 /* mask for CU command */
101 #define IE_CU_NOP 0 /* included for completeness */
102 #define IE_CU_START 0x0100 /* do-command command */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldCOFFThumb.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
105 uint64_t Addend = 0; in processRelocationRef()
148 RelocationEntry RE(SectionID, Offset, RelType, 0, -1, 0, 0, 0, false, 0); in processRelocationRef()
164 TargetOffset, 0, 0, false, 0, IsTargetThumbFun in processRelocationRef()
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