Lines Matching +full:0 +full:x0700
34 #define R12A_RXDW1_AMSDU 0x00002000
35 #define R12A_RXDW1_AMPDU 0x00008000
36 #define R12A_RXDW1_CKSUM_ERR 0x00100000
37 #define R12A_RXDW1_IPV6 0x00200000
38 #define R12A_RXDW1_UDP 0x00400000
39 #define R12A_RXDW1_CKSUM 0x00800000
41 #define R12A_RXDW2_RPT_C2H 0x10000000
43 #define R12A_RXDW3_RATE_M 0x0000007f
44 #define R12A_RXDW3_RATE_S 0
46 #define R12A_RXDW4_SPLCP 0x00000001
47 #define R12A_RXDW4_LDPC 0x00000002
48 #define R12A_RXDW4_STBC 0x00000004
49 #define R12A_RXDW4_BW_M 0x00000030
51 #define R12A_RXDW4_BW20 0
60 #define R12A_PHYW1_CHAN_M 0x03ff
61 #define R12A_PHYW1_CHAN_S 0
62 #define R12A_PHYW1_CHAN_EXT_M 0x3c00
64 #define R12A_PHYW1_RFMOD_M 0xc000
79 #define R12A_PHYW13_ANTIDX_A_M 0x0700
81 #define R12A_PHYW13_ANTIDX_B_M 0x3800