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/freebsd/contrib/file/magic/Magdir/
H A Dhitachi-sh13 # 2nd NTFS filesystem sector often starts with 0x05004e00 for unicode string 5 NTLDR
15 0 beshort 0x0500
16 # test for unused flag bits (0x8000,0x0800,0x0400,0x0200,x0080) in f_flags
17 >18 ubeshort&0x8E80 0
20 >>0 use \^display-coff
23 0 leshort 0x0550
25 >18 uleshort&0x8E80 0
28 >>0 use display-coff
32 0 leshort 0x01a2
33 >16 leshort 0
[all …]
H A Dcoff16 0 name display-coff-processor
18 >0 uleshort 0x014c Intel i386
19 >0 uleshort 0x014d Intel i860
20 >0 uleshort 0x0160 MIPS R3000 (big-endian)
21 >0 uleshort 0x0162 MIPS R3000
22 >0 uleshort 0x0166 MIPS R4000
23 >0 uleshort 0x0168 MIPS R10000
24 >0 uleshort 0x0169 MIPS WCE v2
25 >0 uleshort 0x0184 Alpha 32-bit
26 >0 uleshort 0x01a2 Hitachi SH3
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dapll.txt16 - #clock-cells : from common clock binding; shall be set to 0.
29 #clock-cells = <0>;
31 reg = <0x021c>, <0x0220>;
36 #clock-cells = <0>;
42 reg = <0x0500>, <0x0530>, <0x0520>;
H A Ddpll.txt34 - #clock-cells : from common clock binding; shall be set to 0.
68 #clock-cells = <0>;
71 reg = <0x490>, <0x45c>, <0x488>, <0x468>;
75 #clock-cells = <0>;
81 reg = <0x4>, <0x24>, <0x34>, <0x40>;
85 #clock-cells = <0>;
88 reg = <0x90>, <0x5c>, <0x68>;
92 #clock-cells = <0>;
95 reg = <0x0500>, <0x0540>;
99 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82541.h42 #define IGP01E1000_PHY_AGC_A 0x1172
43 #define IGP01E1000_PHY_AGC_B 0x1272
44 #define IGP01E1000_PHY_AGC_C 0x1472
45 #define IGP01E1000_PHY_AGC_D 0x1872
47 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
48 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
49 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
50 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
52 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
53 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
[all …]
/freebsd/contrib/libpcap/
H A Dethertype.h35 #define ETHERTYPE_PUP 0x0200 /* PUP protocol */
38 #define ETHERTYPE_IP 0x0800 /* IP protocol */
41 #define ETHERTYPE_ARP 0x0806 /* Addr. resolution protocol */
44 #define ETHERTYPE_NS 0x0600
47 #define ETHERTYPE_SPRITE 0x0500
50 #define ETHERTYPE_TRAIL 0x1000
53 #define ETHERTYPE_MOPDL 0x6001
56 #define ETHERTYPE_MOPRC 0x6002
59 #define ETHERTYPE_DN 0x6003
62 #define ETHERTYPE_LAT 0x6004
[all …]
/freebsd/sys/dev/mlx/
H A Dmlxio.h36 #define MLX_SYSD_ONLINE 0x03
37 #define MLX_SYSD_CRITICAL 0x04
38 #define MLX_SYSD_OFFLINE 0xff
49 #define MLX_PAUSE_ALL 0xff
50 #define MLX_PAUSE_CANCEL 0x00
81 #define MLX_REBUILDSTAT_REBUILDCHECK 0x0000
82 #define MLX_REBUILDSTAT_ADDCAPACITY 0x0400
83 #define MLX_REBUILDSTAT_ADDCAPACITYINIT 0x0500
84 #define MLX_REBUILDSTAT_IDLE 0xffff
90 #define MLX_NEXT_CHILD _IOWR('M', 0, int)
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/contrib/tcpdump/
H A Dethertype.h46 #define ETHERTYPE_GRE_ISO 0x00FE /* not really an ethertype only used in GRE */
49 #define ETHERTYPE_PUP 0x0200 /* PUP protocol */
52 #define ETHERTYPE_IP 0x0800 /* IP protocol */
55 #define ETHERTYPE_ARP 0x0806 /* Addr. resolution protocol */
58 #define ETHERTYPE_REVARP 0x8035 /* reverse Addr. resolution protocol */
61 #define ETHERTYPE_NS 0x0600
64 #define ETHERTYPE_SPRITE 0x0500
67 #define ETHERTYPE_TRAIL 0x1000
70 #define ETHERTYPE_MOPDL 0x6001
73 #define ETHERTYPE_MOPRC 0x6002
[all …]
/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_chan.c64 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0); in r21a_bypass_ext_lna_2ghz()
65 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0); in r21a_bypass_ext_lna_2ghz()
66 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07); in r21a_bypass_ext_lna_2ghz()
67 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700); in r21a_bypass_ext_lna_2ghz()
77 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); in r21a_set_band_2ghz()
80 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
81 R12A_RFE_PINMUX_LNA_MASK, 0x7000); in r21a_set_band_2ghz()
82 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
83 R12A_RFE_PINMUX_PA_A_MASK, 0x70); in r21a_set_band_2ghz()
87 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000); in r21a_set_band_2ghz()
[all …]
/freebsd/sys/dev/usb/quirk/
H A Dusb_quirk.c78 .vid = USB_VENDOR_##v, .pid = USB_PRODUCT_##v##_##p, .lo_rev = 0x0000, \
79 .hi_rev = 0xffff, .quirks = { __VA_ARGS__ } \
84 .vid = USB_VENDOR_##v, .pid = 0x0000, .lo_rev = 0x0000, .hi_rev = 0xffff, \
96 USB_QUIRK_REV(INSIDEOUT, EDGEPORT4, 0x094, 0x094, UQ_SWAP_UNICODE),
97 USB_QUIRK_REV(DALLAS, J6502, 0x0a2, 0x0a2, UQ_BAD_ADC),
98 USB_QUIRK_REV(DALLAS, J6502, 0x0a2, 0x0a2, UQ_AU_NO_XU),
99 USB_QUIRK_REV(ALTEC, ADA70, 0x103, 0x103, UQ_BAD_ADC),
100 USB_QUIRK_REV(ALTEC, ASC495, 0x000, 0x000, UQ_BAD_AUDIO),
101 USB_QUIRK_REV(QTRONIX, 980N, 0x110, 0x110, UQ_SPUR_BUT_UP),
102 USB_QUIRK_REV(ALCOR2, KBD_HUB, 0x001, 0x001, UQ_SPUR_BUT_UP),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/dev/vnic/
H A Dnic_reg.h35 #define NIC_PF_CFG (0x0000)
36 #define NIC_PF_STATUS (0x0010)
37 #define NIC_PF_INTR_TIMER_CFG (0x0030)
38 #define NIC_PF_BIST_STATUS (0x0040)
39 #define NIC_PF_SOFT_RESET (0x0050)
40 #define NIC_PF_TCP_TIMER (0x0060)
41 #define NIC_PF_BP_CFG (0x0080)
42 #define NIC_PF_RRM_CFG (0x0088)
43 #define NIC_PF_CQM_CF (0x00A0)
44 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
/freebsd/sys/x86/include/
H A Dapm_bios.h25 #define APM_BIOS 0x53
26 #define APM_INT 0x15
29 #define APM_16BIT_SUPPORT 0x01
30 #define APM_32BIT_SUPPORT 0x02
31 #define APM_CPUIDLE_SLOW 0x04
32 #define APM_DISABLED 0x08
33 #define APM_DISENGAGED 0x10
36 #define APM_OURADDR 0x00080000
39 #define APM_INSTCHECK 0x00
40 #define APM_REALCONNECT 0x01
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x4>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x4>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
/freebsd/sys/ufs/ufs/
H A Dquota.h58 #define USRQUOTA 0 /* element used for user quotas */
77 #define SUBCMDMASK 0x00ff
81 #define Q_QUOTAON 0x0100 /* enable quotas */
82 #define Q_QUOTAOFF 0x0200 /* disable quotas */
83 #define Q_GETQUOTA32 0x0300 /* get limits and usage (32-bit version) */
84 #define Q_SETQUOTA32 0x0400 /* set limits and usage (32-bit version) */
85 #define Q_SETUSE32 0x0500 /* set usage (32-bit version) */
86 #define Q_SYNC 0x0600 /* sync disk copy of a filesystems quotas */
87 #define Q_GETQUOTA 0x0700 /* get limits and usage (64-bit version) */
88 #define Q_SETQUOTA 0x0800 /* set limits and usage (64-bit version) */
[all …]
/freebsd/sys/dev/sound/usb/
H A Duaudioreg.h38 #define UAUDIO_VERSION_10 0x0100
39 #define UAUDIO_VERSION_20 0x0200
40 #define UAUDIO_VERSION_30 0x0300
42 #define UAUDIO_PROTOCOL_20 0x20
44 #define UDESC_CS_UNDEFINED 0x20
45 #define UDESC_CS_DEVICE 0x21
46 #define UDESC_CS_CONFIG 0x22
47 #define UDESC_CS_STRING 0x23
48 #define UDESC_CS_INTERFACE 0x24
49 #define UDESC_CS_ENDPOINT 0x25
[all …]
/freebsd/sys/dev/iwi/
H A Dif_iwireg.h38 #define IWI_CSR_INTR 0x0008
39 #define IWI_CSR_INTR_MASK 0x000c
40 #define IWI_CSR_INDIRECT_ADDR 0x0010
41 #define IWI_CSR_INDIRECT_DATA 0x0014
42 #define IWI_CSR_AUTOINC_ADDR 0x0018
43 #define IWI_CSR_AUTOINC_DATA 0x001c
44 #define IWI_CSR_RST 0x0020
45 #define IWI_CSR_CTL 0x0024
46 #define IWI_CSR_IO 0x0030
47 #define IWI_CSR_CMD_BASE 0x0200
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]

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