64 	rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0);  in r21a_bypass_ext_lna_2ghz()
65 	rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0);  in r21a_bypass_ext_lna_2ghz()
66 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07);  in r21a_bypass_ext_lna_2ghz()
67 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700);  in r21a_bypass_ext_lna_2ghz()
77 	    0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM);  in r21a_set_band_2ghz()
80 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),  in r21a_set_band_2ghz()
81 	    R12A_RFE_PINMUX_LNA_MASK, 0x7000);  in r21a_set_band_2ghz()
82 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),  in r21a_set_band_2ghz()
83 	    R12A_RFE_PINMUX_PA_A_MASK, 0x70);  in r21a_set_band_2ghz()
87 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000);  in r21a_set_band_2ghz()
88 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0);  in r21a_set_band_2ghz()
89 		rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0x05, 0x02);  in r21a_set_band_2ghz()
90 		rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0x0500, 0x0200);  in r21a_set_band_2ghz()
97 	rtwn_bb_setbits(sc, R12A_TX_SCALE(0), 0x0f00, 0);  in r21a_set_band_2ghz()
99 	rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);  in r21a_set_band_2ghz()
100 	rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);  in r21a_set_band_2ghz()
105 	rtwn_write_1(sc, R12A_CCK_CHECK, 0);  in r21a_set_band_2ghz()
114 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),  in r21a_set_band_5ghz()
115 	    R12A_RFE_PINMUX_LNA_MASK, 0x5000);  in r21a_set_band_5ghz()
116 	rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0),  in r21a_set_band_5ghz()
117 	    R12A_RFE_PINMUX_PA_A_MASK, 0x40);  in r21a_set_band_5ghz()
126 	for (ntries = 0; ntries < 100; ntries++) {  in r21a_set_band_5ghz()
127 		if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)  in r21a_set_band_5ghz()
143 	rtwn_bb_setbits(sc, R12A_TX_SCALE(0), 0x0f00, 0x0100);  in r21a_set_band_5ghz()
145 	rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);  in r21a_set_band_5ghz()
146 	rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);  in r21a_set_band_5ghz()