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/freebsd/crypto/openssl/crypto/conf/
H A Dconf_def.h43 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
44 0x0000, 0x0010, 0x0010, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
47 0x0010, 0x0200, 0x0040, 0x0080, 0x1000, 0x0200, 0x0200, 0x0040,
48 0x0000, 0x0000, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200,
49 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
50 0x0001, 0x0001, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x0200,
51 0x0200, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
52 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
[all …]
/freebsd/sys/dev/mii/
H A Dip1000phyreg.h38 #define IP1000PHY_MII_BMCR 0x00
39 #define IP1000PHY_BMCR_FDX 0x0100
40 #define IP1000PHY_BMCR_STARTNEG 0x0200
41 #define IP1000PHY_BMCR_ISO 0x0400
42 #define IP1000PHY_BMCR_PDOWN 0x0800
43 #define IP1000PHY_BMCR_AUTOEN 0x1000
44 #define IP1000PHY_BMCR_LOOP 0x4000
45 #define IP1000PHY_BMCR_RESET 0x8000
47 #define IP1000PHY_BMCR_10 0x0000
48 #define IP1000PHY_BMCR_100 0x2000
[all …]
H A De1000phyreg.h72 #define E1000_MAX_REG_ADDRESS 0x1F
74 #define E1000_CR 0x00 /* control register */
75 #define E1000_CR_SPEED_SELECT_MSB 0x0040
76 #define E1000_CR_COLL_TEST_ENABLE 0x0080
77 #define E1000_CR_FULL_DUPLEX 0x0100
78 #define E1000_CR_RESTART_AUTO_NEG 0x0200
79 #define E1000_CR_ISOLATE 0x0400
80 #define E1000_CR_POWER_DOWN 0x0800
81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
82 #define E1000_CR_SPEED_SELECT_LSB 0x2000
[all …]
H A Dciphyreg.h44 #define CIPHY_MII_BMCR 0x00
45 #define CIPHY_BMCR_RESET 0x8000
46 #define CIPHY_BMCR_LOOP 0x4000
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
48 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
49 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
50 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
51 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
[all …]
H A Dnsphyterreg.h44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
45 #define PHYSTS_REL 0x8000 /* receive error latch */
46 #define PHYSTS_CIML 0x4000 /* CIM latch */
47 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
48 #define PHYSTS_DEVRDY 0x0800 /* device ready */
49 #define PHYSTS_PGRX 0x0400 /* page received */
50 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
51 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
52 #define PHYSTS_REMFAULT 0x0080 /* remote fault */
53 #define PHYSTS_JABBER 0x0040 /* jabber detect */
[all …]
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Drgephyreg.h47 #define RGEPHY_MII_BMCR 0x00
48 #define RGEPHY_BMCR_RESET 0x8000
49 #define RGEPHY_BMCR_LOOP 0x4000
50 #define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
51 #define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
52 #define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */
53 #define RGEPHY_BMCR_ISO 0x0400 /* Isolate */
54 #define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
55 #define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
56 #define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dmii.h45 #define MII_COMMAND_START 0x01
46 #define MII_COMMAND_READ 0x02
47 #define MII_COMMAND_WRITE 0x01
48 #define MII_COMMAND_ACK 0x02
50 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
51 #define BMCR_RESET 0x8000 /* reset */
52 #define BMCR_LOOP 0x4000 /* loopback */
53 #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */
54 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */
55 #define BMCR_PDOWN 0x0800 /* power down */
[all …]
H A Dtdkphyreg.h39 #define VENDOR_RXCC 0x0001
40 #define VENDOR_PCSBP 0x0002
41 #define VENDOR_RVSPOL 0x0010
42 #define VENDOR_NOAPOL 0x0020
43 #define VENDOR_GPIO0DIR 0x0040
44 #define VENDOR_GPIO0DAT 0x0080
45 #define VENDOR_GPIO1DIR 0x0100
46 #define VENDOR_GPIO1DAT 0x0200
47 #define VENDOR_10BTLOOP 0x0400
48 #define VENDOR_NOSQE 0x0800
[all …]
H A Drdcphyreg.h33 #define MII_RDCPHY_DEBUG 0x11
34 #define DEBUG_JABBER_DIS 0x0040
35 #define DEBUG_LOOP_BACK_10MBPS 0x0400
37 #define MII_RDCPHY_CTRL 0x14
38 #define CTRL_SQE_ENB 0x0100
39 #define CTRL_NEG_POLARITY 0x0400
40 #define CTRL_AUTO_POLARITY 0x0800
41 #define CTRL_MDIXSEL_RX 0x2000
42 #define CTRL_MDIXSEL_TX 0x4000
43 #define CTRL_AUTO_MDIX_DIS 0x8000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x4>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x4>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
H A Domap2420-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
37 reg = <0x0070>;
42 #clock-cells = <0>;
46 reg = <0x0810>;
50 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/vdev_disk/
H A Dpage_alignment.c65 * physical (order-0) page boundary, as the kernel expects to be able in vdev_disk_check_alignment_cb()
104 return (0); in vdev_disk_check_alignment_cb()
125 512, 0x1000, {
126 { 0x0, 0x1000 },
130 512, 0x400, {
131 { 0x0, 0x1000 },
135 512, 0x400, {
136 { 0x0c00, 0x0400 },
140 512, 0x400, {
141 { 0x0200, 0x0e00 },
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmediatek,mt8186-pinctrl.yaml229 reg = <0x10005000 0x1000>,
230 <0x10002000 0x0200>,
231 <0x10002200 0x0200>,
232 <0x10002400 0x0200>,
233 <0x10002600 0x0200>,
234 <0x10002A00 0x0200>,
235 <0x10002c00 0x0200>,
236 <0x1000b000 0x1000>;
242 gpio-ranges = <&pio 0 0 185>;
244 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dpinctrl-mt8186.yaml230 reg = <0x10005000 0x1000>,
231 <0x10002000 0x0200>,
232 <0x10002200 0x0200>,
233 <0x10002400 0x0200>,
234 <0x10002600 0x0200>,
235 <0x10002A00 0x0200>,
236 <0x10002c00 0x0200>,
237 <0x1000b000 0x1000>;
243 gpio-ranges = <&pio 0 0 185>;
245 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
/freebsd/sys/dev/usb/net/
H A Dif_axereg.h46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
[all …]
/freebsd/sys/dev/vte/
H A Dif_vtereg.h36 #define VENDORID_RDC 0x17F3
41 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
43 /* MAC control register 0 */
44 #define VTE_MCR0 0x00
45 #define MCR0_ACCPT_ERR 0x0001
46 #define MCR0_RX_ENB 0x0002
47 #define MCR0_ACCPT_RUNT 0x0004
48 #define MCR0_ACCPT_LONG_PKT 0x0008
49 #define MCR0_ACCPT_DRIBBLE 0x0010
50 #define MCR0_PROMISC 0x0020
[all …]
/freebsd/sys/dev/ste/
H A Dif_stereg.h39 #define ST_VENDORID 0x13F0
40 #define ST_DEVICEID_ST201_1 0x0200
41 #define ST_DEVICEID_ST201_2 0x0201
46 #define DL_VENDORID 0x1186
47 #define DL_DEVICEID_DL10050 0x1002
56 #define STE_DMACTL 0x00
57 #define STE_TX_DMALIST_PTR 0x04
58 #define STE_TX_DMABURST_THRESH 0x08
59 #define STE_TX_DMAURG_THRESH 0x09
60 #define STE_TX_DMAPOLL_PERIOD 0x0A
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dusb-drd.yaml19 0x0200 or above.
21 enum: [0x0100, 0x0120, 0x0130, 0x0200]
71 reg = <0x4a030000 0xcfff>;
72 interrupts = <0 92 4>;
77 otg-rev = <0x0200>;
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/sys/dev/le/
H A Dlancereg.h139 #define LE_CSR0 0x0000 /* Control and status register */
140 #define LE_CSR1 0x0001 /* low address of init block */
141 #define LE_CSR2 0x0002 /* high address of init block */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
[all …]

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