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/linux/arch/arm/boot/dts/cirrus/
H A Dep93xx-bk3.dts17 memory@0 {
20 reg = <0x00000000 0x02000000>,
21 <0x000530c0 0x01fdd000>;
26 led-0 {
28 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
44 reg = <0x60000000 0x8000000>;
46 #size-cells = <0>;
48 nand@0 {
49 reg = <0>;
55 partition@0 {
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c39 #define TRANSFER_RAM_MASK 0x001c0000
102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode()
104 for (i = 0; i < fw_size; i++) in imu_v12_0_load_microcode()
105 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
107 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode()
116 for (i = 0; i < fw_size; i++) in imu_v12_0_load_microcode()
117 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
119 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
121 return 0; in imu_v12_0_load_microcode()
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/linux/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-frontend.yaml63 port@0:
94 reg = <0x01e00000 0x20000>;
104 #size-cells = <0>;
108 #size-cells = <0>;
111 fe0_out_be0: endpoint@0 {
112 reg = <0>;
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi11 cpu0_opp_table: opp-table-0 {
101 reg = <0 0xfc000000 0 0x1000>;
108 ports-implemented = <0x1>;
115 reg = <0x0 0xfdc70000 0x0 0x1000>;
120 reg = <0x0 0xfe190080 0x0 0x20>;
125 reg = <0x0 0xfe190100 0x0 0x20>;
130 reg = <0x0 0xfe190200 0x0 0x20>;
135 reg = <0x0 0xfdcb8000 0x0 0x10000>;
140 reg = <0x0 0xfe8c0000 0x0 0x20000>;
141 #phy-cells = <0>;
[all …]
H A Drk356x-base.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
59 i-cache-size = <0x8000>;
62 d-cache-size = <0x8000>;
71 reg = <0x0 0x100>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
86 reg = <0x0 0x200>;
[all …]
/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c37 for (i = 0; i < 64; i++) { in gk104_top_parse()
41 type = ~0; in gk104_top_parse()
42 inst = 0; in gk104_top_parse()
45 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_parse()
47 switch (data & 0x00000003) { in gk104_top_parse()
48 case 0x00000000: /* NOT_VALID */ in gk104_top_parse()
50 case 0x00000001: /* DATA */ in gk104_top_parse()
51 inst = (data & 0x3c000000) >> 26; in gk104_top_parse()
52 info->addr = (data & 0x00fff000); in gk104_top_parse()
53 if (data & 0x00000004) in gk104_top_parse()
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
80 reg = <0x01c00000 0x1000>;
87 reg = <0x00018000 0x1c000>;
90 ranges = <0 0x00018000 0x1c000>;
92 ve_sram: sram-section@0 {
95 reg = <0x000000 0x1c000>;
102 reg = <0x01c0e000 0x1000>;
113 reg = <0x01c15000 0x1000>;
[all …]
/linux/include/soc/fsl/qe/
H A Dqe.h34 QE_CLK_NONE = 0,
150 return 0; in cpm_muram_dma()
245 return 0; in qe_alive_during_sleep()
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
304 __be32 traps[16]; /* Trap addresses, 0 == ignore */
348 #define BD_STATUS_MASK 0xffff0000
349 #define BD_LENGTH_MASK 0x0000ffff
357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/linux/drivers/macintosh/
H A Dwindfarm_pm91.c57 #define DBG(args...) do { } while(0)
83 #define FAILURE_FAN 0x01
84 #define FAILURE_SENSOR 0x02
85 #define FAILURE_OVERTEMP 0x04
160 /* Get the FVT params for operating point 0 (the only supported one in wf_smu_create_cpu_fans()
168 tmax = 0x5e0000; /* 94 degree default */ in wf_smu_create_cpu_fans()
224 if (--st->ticks != 0) { in wf_smu_cpu_fans_tick()
251 if (temp > 0x4a0000) in wf_smu_cpu_fans_tick()
265 if (fan_cpu_main && wf_smu_failure_state == 0) { in wf_smu_cpu_fans_tick()
273 if (fan_cpu_second && wf_smu_failure_state == 0) { in wf_smu_cpu_fans_tick()
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun6i-a31.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
213 #clock-cells = <0>;
221 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
252 #clock-cells = <0>;
254 reg = <0x01c200d0 0x4>;
274 reg = <0x01c02000 0x1000>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
58 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
76 reg = <0x0 0x3>;
85 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
/linux/drivers/ata/
H A Dpata_macio.c45 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
75 #define IDE_TIMING_CONFIG 0x200
76 #define IDE_INTERRUPT 0x300
79 #define IDE_KAUAI_PIO_CONFIG 0x200
80 #define IDE_KAUAI_ULTRA_CONFIG 0x210
81 #define IDE_KAUAI_POLL_CONFIG 0x220
98 #define TR_133_PIOREG_PIO_MASK 0xff000fff
99 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
100 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
101 #define TR_133_UDMAREG_UDMA_EN 0x00000001
[all …]
/linux/drivers/usb/gadget/udc/
H A Dudc-xilinx.c28 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */
29 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */
30 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */
31 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */
32 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */
33 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */
34 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */
35 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */
36 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */
37 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c37 #define NV_CIO_CRE_44_HEADA 0x0
38 #define NV_CIO_CRE_44_HEADB 0x3
39 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
53 uint8_t sum = 0; in nv_cksum()
55 for (i = 0; i < length; i++) in nv_cksum()
66 int compare_record_len, i = 0; in clkcmptable()
67 uint16_t compareclk, scriptptr = 0; in clkcmptable()
96 NV_INFO(drm, "0x%04X: Parsing digital output script table\n", in run_digital_op_script()
98 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB : in run_digital_op_script()
109 …bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0); in call_lvds_manufacturer_script()
[all …]

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