28 #define XUSB_EP0_CONFIG_OFFSET		0x0000  /* EP0 Config Reg Offset */
29 #define XUSB_SETUP_PKT_ADDR_OFFSET	0x0080  /* Setup Packet Address */
30 #define XUSB_ADDRESS_OFFSET		0x0100  /* Address Register */
31 #define XUSB_CONTROL_OFFSET		0x0104  /* Control Register */
32 #define XUSB_STATUS_OFFSET		0x0108  /* Status Register */
33 #define XUSB_FRAMENUM_OFFSET		0x010C	/* Frame Number Register */
34 #define XUSB_IER_OFFSET			0x0110	/* Interrupt Enable Register */
35 #define XUSB_BUFFREADY_OFFSET		0x0114	/* Buffer Ready Register */
36 #define XUSB_TESTMODE_OFFSET		0x0118	/* Test Mode Register */
37 #define XUSB_DMA_RESET_OFFSET		0x0200  /* DMA Soft Reset Register */
38 #define XUSB_DMA_CONTROL_OFFSET		0x0204	/* DMA Control Register */
39 #define XUSB_DMA_DSAR_ADDR_OFFSET	0x0208	/* DMA source Address Reg */
40 #define XUSB_DMA_DDAR_ADDR_OFFSET	0x020C	/* DMA destination Addr Reg */
41 #define XUSB_DMA_LENGTH_OFFSET		0x0210	/* DMA Length Register */
42 #define XUSB_DMA_STATUS_OFFSET		0x0214	/* DMA Status Register */
45 #define XUSB_EP_CFGSTATUS_OFFSET	0x00	/* Endpoint Config Status  */
46 #define XUSB_EP_BUF0COUNT_OFFSET	0x08	/* Buffer 0 Count */
47 #define XUSB_EP_BUF1COUNT_OFFSET	0x0C	/* Buffer 1 Count */
49 #define XUSB_CONTROL_USB_READY_MASK	0x80000000 /* USB ready Mask */
50 #define XUSB_CONTROL_USB_RMTWAKE_MASK	0x40000000 /* Remote wake up mask */
53 #define XUSB_STATUS_GLOBAL_INTR_MASK	0x80000000 /* Global Intr Enable */
54 #define XUSB_STATUS_DMADONE_MASK	0x04000000 /* DMA done Mask */
55 #define XUSB_STATUS_DMAERR_MASK		0x02000000 /* DMA Error Mask */
56 #define XUSB_STATUS_DMABUSY_MASK	0x80000000 /* DMA Error Mask */
57 #define XUSB_STATUS_RESUME_MASK		0x01000000 /* USB Resume Mask */
58 #define XUSB_STATUS_RESET_MASK		0x00800000 /* USB Reset Mask */
59 #define XUSB_STATUS_SUSPEND_MASK	0x00400000 /* USB Suspend Mask */
60 #define XUSB_STATUS_DISCONNECT_MASK	0x00200000 /* USB Disconnect Mask */
61 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK	0x00100000 /* FIFO Buff Ready Mask */
62 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK	0x00080000 /* FIFO Buff Free Mask */
63 #define XUSB_STATUS_SETUP_PACKET_MASK	0x00040000 /* Setup packet received */
64 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK	0x00000200 /* EP 1 Buff 2 Processed */
65 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK	0x00000002 /* EP 1 Buff 1 Processed */
66 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK	0x00000100 /* EP 0 Buff 2 Processed */
67 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK	0x00000001 /* EP 0 Buff 1 Processed */
68 #define XUSB_STATUS_HIGH_SPEED_MASK	0x00010000 /* USB Speed Mask */
70 #define XUSB_STATUS_INTR_EVENT_MASK	0x01E00000
72 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK	0x0000FEFF
73 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */
74 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK	0x00000101
78 #define XUSB_EP_CFG_VALID_MASK		0x80000000 /* Endpoint Valid bit */
79 #define XUSB_EP_CFG_STALL_MASK		0x40000000 /* Endpoint Stall bit */
80 #define XUSB_EP_CFG_DATA_TOGGLE_MASK	0x08000000 /* Endpoint Data toggle */
84 #define XUSB_EP_NUMBER_ZERO		0	/* End point Zero */
86 #define XUSB_DMA_READ_FROM_DPRAM	0x80000000
87 #define XUSB_DMA_DMASR_BUSY		0x80000000 /* DMA busy */
88 #define XUSB_DMA_DMASR_ERROR		0x40000000 /* DMA Error */
93 #define XUSB_DMA_BRR_CTRL		0x40000000 /* DMA bufready ctrl bit */
95 #define SETUP_PHASE			0x0000	/* Setup Phase */
96 #define DATA_PHASE			0x0001  /* Data Phase */
97 #define STATUS_PHASE			0x0002  /* Status Phase */
99 #define EP0_MAX_PACKET		64 /* Endpoint 0 maximum packet length */
198 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
199 			  0x1600 };
267 	udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);  in xudc_wrstatus()
311  * Return: 0 on success, error code on failure
320 	int rc = 0;  in xudc_start_dma()
371  * Return: 0 on success, -EAGAIN if no buffer is free and error
409 		ep->curbufnum = 0;  in xudc_dma_send()
425  * Return: 0 on success, -EAGAIN if no buffer is free and error
458 		ep->curbufnum = 0;  in xudc_dma_receive()
474  * Return: 0 on success, -EAGAIN if no buffer is free.
484 	int rc = 0;  in xudc_eptxrx()
534 		ep->curbufnum = 0;  in xudc_eptxrx()
582  * Return: 0 if request is completed and -EAGAIN if not completed.
591 	u8 two_pkts = 0;  in xudc_read_fifo()
627 		return 0;  in xudc_read_fifo()
632 	case 0:  in xudc_read_fifo()
645 			xudc_done(ep, req, 0);  in xudc_read_fifo()
646 			return 0;  in xudc_read_fifo()
649 			two_pkts = 0;  in xudc_read_fifo()
660 		retval = 0;  in xudc_read_fifo()
672  * Return: 0 if request is completed and -EAGAIN if not completed.
683 	int is_last, is_short = 0;  in xudc_write_fifo()
694 	case 0:  in xudc_write_fifo()
701 				is_last = 0;  in xudc_write_fifo()
711 			xudc_done(ep, req, 0);  in xudc_write_fifo()
712 			retval = 0;  in xudc_write_fifo()
722 		retval = 0;  in xudc_write_fifo()
749  * Return: 0 for success and error value on failure
795 	return 0;  in xudc_ep_set_halt()
803  * Return: 0 for success and error value on failure
814 	ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);  in __xudc_ep_enable()
815 	/* Bit 3...0:endpoint number */  in __xudc_ep_enable()
826 		ep->is_iso = 0;  in __xudc_ep_enable()
830 		ep->is_iso = 0;  in __xudc_ep_enable()
838 		ep->is_iso = 0;  in __xudc_ep_enable()
853 	ep->curbufnum = 0;  in __xudc_ep_enable()
883 	return 0;  in __xudc_ep_enable()
891  * Return: 0 for success and error value on failure
925  * Return: 0 for success and error value on failure
957 	return 0;  in xudc_ep_disable()
995  * __xudc_ep0_queue - Adds the request to endpoint 0 queue.
996  * @ep0: pointer to the xusb endpoint 0 structure.
999  * Return: 0 for success and error value on failure
1017 	req->usb_req.actual = 0;  in __xudc_ep0_queue()
1034 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);  in __xudc_ep0_queue()
1041 	return 0;  in __xudc_ep0_queue()
1045  * xudc_ep0_queue - Adds the request to endpoint 0 queue.
1046  * @_ep: pointer to the usb endpoint 0 structure.
1050  * Return: 0 for success and error value on failure
1074  * Return: 0 for success and error value on failure
1099 	_req->actual = 0;  in xudc_ep_queue()
1128 	return 0;  in xudc_ep_queue()
1136  * Return: 0 for success and error value on failure
1161 	return 0;  in xudc_ep_dequeue()
1171  * endpoint 0 enable should not be called by gadget layer.
1185  * endpoint 0 disable should not be called by gadget layer.
1235  * Return: 0 on success and error on failure
1262 	status = 0;  in xudc_wakeup()
1273  * Return: 0 always
1295 	return 0;  in xudc_pullup()
1308 	for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) {  in xudc_eps_init()
1315 						  (unsigned short) ~0);  in xudc_eps_init()
1339 		 * each endpoint is 0x10.  in xudc_eps_init()
1341 		ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10);  in xudc_eps_init()
1342 		ep->is_in = 0;  in xudc_eps_init()
1343 		ep->is_iso = 0;  in xudc_eps_init()
1344 		ep->maxpacket = 0;  in xudc_eps_init()
1361 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {  in xudc_stop_activity()
1381 	int ret = 0;  in xudc_start()
1399 	/* Set device address and remote wakeup to 0 */  in xudc_start()
1400 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_start()
1401 	udc->remote_wkp = 0;  in xudc_start()
1423 	/* Set device address and remote wakeup to 0 */  in xudc_stop()
1424 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_stop()
1425 	udc->remote_wkp = 0;  in xudc_stop()
1431 	return 0;  in xudc_stop()
1452 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {  in xudc_clear_stall_all_ep()
1488 		udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);  in xudc_startup_handler()
1490 		/* Set device address and remote wakeup to 0 */  in xudc_startup_handler()
1491 		udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_startup_handler()
1492 		udc->remote_wkp = 0;  in xudc_startup_handler()
1532 		udc->usb_state = 0;  in xudc_startup_handler()
1582 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_setaddress()
1586 	req->usb_req.length = 0;  in xudc_setaddress()
1588 	if (ret == 0)  in xudc_setaddress()
1603 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_getstatus()
1606 	u16 status = 0;  in xudc_getstatus()
1645 	if (ret == 0)  in xudc_getstatus()
1660 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_set_clear_feature()
1666 	int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0);  in xudc_set_clear_feature()
1682 				udc->remote_wkp = 0;  in xudc_set_clear_feature()
1735 	req->usb_req.length = 0;  in xudc_set_clear_feature()
1737 	if (ret == 0)  in xudc_set_clear_feature()
1753 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_handle_setup()
1808 	if (udc->driver->setup(&udc->gadget, &setup) < 0)  in xudc_handle_setup()
1814  * xudc_ep0_out - Processes the endpoint 0 OUT token.
1819 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_ep0_out()
1836 		xudc_done(ep0, req, 0);  in xudc_ep0_out()
1853 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);  in xudc_ep0_out()
1863  * xudc_ep0_in - Processes the endpoint 0 IN token.
1868 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_ep0_in()
1873 	u16 count = 0;  in xudc_ep0_in()
1901 		xudc_done(ep0, req, 0);  in xudc_ep0_in()
1933  * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler.
1935  * @intrstatus:	It's the mask value for the interrupt sources on endpoint 0.
1957  *		than endpoint 0.
1971 		ep->buffer0ready = 0;  in xudc_nonctrl_ep_handler()
2058  * Return: 0 for success and error value on failure
2087 	udc->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in xudc_probe()
2091 	irq = platform_get_irq(pdev, 0);  in xudc_probe()
2092 	if (irq < 0)  in xudc_probe()
2094 	ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0,  in xudc_probe()
2096 	if (ret < 0) {  in xudc_probe()
2142 	udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);  in xudc_probe()
2146 	/* Set device address to 0.*/  in xudc_probe()
2147 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_probe()
2165 	dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n",  in xudc_probe()
2169 	return 0;  in xudc_probe()
2212 	return 0;  in xudc_suspend()
2225 	if (ret < 0)  in xudc_resume()
2237 	return 0;  in xudc_resume()