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/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk.c16 #define RTW8852B_RXDCK_VER 0x1
17 #define RTW8852B_IQK_VER 0x2a
22 #define RTW8852B_DPK_VER 0x0d
28 #define DPK_TXAGC_LOWER 0x2e
29 #define DPK_TXAGC_UPPER 0x3f
30 #define DPK_TXAGC_INVAL 0xff
31 #define RFREG_MASKRXBB 0x003e0
32 #define RFREG_MASKMODE 0xf0000
35 LBK_RXIQK = 0x06,
36 SYNC = 0x1
[all...]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
H A Dar9462_2p0_initvals.h34 {0x00001030, 0x00000268, 0x000004d0},
35 {0x00001070, 0x0000018c, 0x00000318},
36 {0x000010b0, 0x00000fd0, 0x00001fa0},
37 {0x00008014, 0x044c044c, 0x08980898},
38 {0x0000801c, 0x148ec02b, 0x148ec057},
39 {0x00008318, 0x000044c0, 0x00008980},
40 {0x00009e00, 0x0372131c, 0x0372131c},
41 {0x0000a230, 0x0000400b, 0x00004016},
42 {0x0000a254, 0x00000898, 0x00001130},
47 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
[all …]
H A Dar9300_jupiter10.ini86 { 0x00000008 , 0x00000000 },
87 { 0x00000030 , 0x00060085 },
88 { 0x00000034 , 0x00000005 },
89 { 0x00000040 , 0x00000000 },
90 { 0x00000044 , 0x00000000 },
91 { 0x00000048 , 0x00000008 },
92 { 0x0000004c , 0x00000010 },
93 { 0x00000050 , 0x00000000 },
94 { 0x00001040 , 0x002ffc0f },
95 { 0x00001044 , 0x002ffc0f },
[all …]
H A Dar9300_jupiter20.ini107 { 0x00001030 , 0x00000268 , 0x000004d0 },
108 { 0x00001070 , 0x0000018c , 0x00000318 },
109 { 0x000010b0 , 0x00000fd0 , 0x00001fa0 },
110 { 0x00008014 , 0x044c044c , 0x08980898 },
111 { 0x0000801c , 0x148ec02b , 0x148ec057 },
112 { 0x00008318 , 0x000044c0 , 0x00008980 },
113 { 0x00009e00 , 0x0372131c , 0x0372131c },
114 { 0x0000a230 , 0x0000400b , 0x00004016 },
115 { 0x0000a254 , 0x00000898 , 0x00001130 },
120 { 0x00018c00 , 0x18253ede },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-nano.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
29 gpios = <&gpio1 5 0>;
37 pinctrl-0 = <&misc_pins>;
162 pinctrl-0 = <&uart0_pins>;
168 pinctrl-0 = <&uart1_pins>;
179 pinctrl-0 = <&uart2_pins>;
189 pinctrl-0 = <&uart3_pins>;
200 pinctrl-0 = <&uart4_pins>;
211 pinctrl-0 = <&uart5_pins>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dboss.ini20 { 0x00000030, 0x00000015, 0x00000015, 0x0000001d, 0x00000015 },
21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/xz-embedded/linux/lib/xz/
H A Dxz_dec_bcj.c68 * PowerPC 4 0
69 * IA-64 16 0
70 * ARM 4 0
72 * SPARC 4 0
85 return b == 0x00 || b == 0xFF; in bcj_x86_test_msbyte()
93 static const uint8_t mask_to_bit_num[8] = { 0, 1, 2, 2, 3, 3, 3, 3 }; in bcj_x86()
104 return 0; in bcj_x86()
107 for (i = 0; i < size; ++i) { in bcj_x86()
108 if ((buf[i] & 0xFE) != 0xE8) in bcj_x86()
113 prev_mask = 0; in bcj_x86()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCPreEmitPeephole.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
138 // LI target-flags(ppc-lo) %const.0). in removeRedundantLIs()
141 assert(BBI->getOperand(0).isReg() && in removeRedundantLIs()
146 Register Reg = BBI->getOperand(0).getReg(); in removeRedundantLIs()
149 if (BBI->getOperand(0).isDead()) { in removeRedundantLIs()
150 DeadOrKillToUnset = &BBI->getOperand(0); in removeRedundantLIs()
186 assert(AfterBBI->getOperand(0).isReg() && in removeRedundantLIs()
232 const MachineOperand &LoadedAddressReg = Instr.getOperand(0); in isGOTPLDpc()
274 BBI->getOperand(0).getReg(), in addLinkerOpt()
287 for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) { in addLinkerOpt()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_s2m.h59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
63 /* [0x8] Descriptor read master configuration */
65 /* [0xc] Descriptor read master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Completion descriptors write master configuration */
77 /* [0x24] AXI outstanding read configuration */
[all …]
H A Dal_hal_udma_regs_m2s.h59 /* [0x0] Completion write master configuration */
61 /* [0x4] Completion write master configuration */
63 /* [0x8] Data read master configuration */
65 /* [0xc] Data read master configuration */
67 /* [0x10] Descriptor read master configuration */
69 /* [0x14] Descriptor read master configuration */
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Descriptors write master configuration (completion) */
77 /* [0x24] AXI outstanding configuration */
[all …]
/freebsd/contrib/bearssl/src/ec/
H A Dec_prime_i31.c34 0x00000108,
35 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x00000007,
36 0x00000000, 0x00000000, 0x00000040, 0x7FFFFF80,
37 0x000000FF
41 0x00000108,
42 0x00014000, 0x00018000, 0x00000000, 0x7FF40000,
43 0x7FEFFFFF, 0x7FF7FFFF, 0x7FAFFFFF, 0x005FFFFF,
44 0x00000000
48 0x00000108,
49 0x6FEE1803, 0x6229C4BD, 0x21B139BE, 0x327150AA,
[all …]
/freebsd/sys/dev/e1000/
H A De1000_defines.h44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/igc/
H A Digc_defines.h16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_type.h82 #define IXGBE_INTEL_VENDOR_ID 0x8086
85 #define IXGBE_DEV_ID_82598 0x10B6
86 #define IXGBE_DEV_ID_82598_BX 0x1508
87 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
88 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
89 #define IXGBE_DEV_ID_82598AT 0x10C8
90 #define IXGBE_DEV_ID_82598AT2 0x150B
91 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
92 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
93 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
[all …]
/freebsd/contrib/libarchive/libarchive/
H A Darchive_read_support_format_cab.c150 #define CFHEADER_signature 0
165 #define CFFOLDER_coffCabStart 0
171 #define CFFILE_cbFile 0
178 #define CFDATA_csum 0
215 #define COMPTYPE_NONE 0x0000
216 #define COMPTYPE_MSZIP 0x0001
217 #define COMPTYPE_QUANTUM 0x0002
218 #define COMPTYPE_LZX 0x0003
233 #define iFoldCONTINUED_FROM_PREV 0xFFFD
234 #define iFoldCONTINUED_TO_NEXT 0xFFFE
[all …]
H A Darchive_read_support_format_rar.c53 #define MARK_HEAD 0x72
54 #define MAIN_HEAD 0x73
55 #define FILE_HEAD 0x74
56 #define COMM_HEAD 0x75
57 #define AV_HEAD 0x76
58 #define SUB_HEAD 0x77
59 #define PROTECT_HEAD 0x78
60 #define SIGN_HEAD 0x79
61 #define NEWSUB_HEAD 0x7a
62 #define ENDARC_HEAD 0x7b
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd/sys/arm64/include/
H A Darmreg.h39 #define MRS_MASK 0xfff00000
40 #define MRS_VALUE 0xd5300000
41 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0)
42 #define MRS_REGISTER(insn) ((insn) & 0x0000001f)
44 #define MRS_Op0_MASK 0x00080000
46 #define MRS_Op1_MASK 0x00070000
48 #define MRS_CRn_MASK 0x0000f000
50 #define MRS_CRm_MASK 0x00000f00
52 #define MRS_Op2_MASK 0x000000e0
53 #define MRS_Rt_SHIFT 0
[all …]