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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/freebsd/sys/dev/mii/
H A De1000phyreg.h72 #define E1000_MAX_REG_ADDRESS 0x1F
74 #define E1000_CR 0x00 /* control register */
75 #define E1000_CR_SPEED_SELECT_MSB 0x0040
76 #define E1000_CR_COLL_TEST_ENABLE 0x0080
77 #define E1000_CR_FULL_DUPLEX 0x0100
78 #define E1000_CR_RESTART_AUTO_NEG 0x0200
79 #define E1000_CR_ISOLATE 0x0400
80 #define E1000_CR_POWER_DOWN 0x0800
81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
82 #define E1000_CR_SPEED_SELECT_LSB 0x2000
[all …]
H A Dip1000phyreg.h38 #define IP1000PHY_MII_BMCR 0x00
39 #define IP1000PHY_BMCR_FDX 0x0100
40 #define IP1000PHY_BMCR_STARTNEG 0x0200
41 #define IP1000PHY_BMCR_ISO 0x0400
42 #define IP1000PHY_BMCR_PDOWN 0x0800
43 #define IP1000PHY_BMCR_AUTOEN 0x1000
44 #define IP1000PHY_BMCR_LOOP 0x4000
45 #define IP1000PHY_BMCR_RESET 0x8000
47 #define IP1000PHY_BMCR_10 0x0000
48 #define IP1000PHY_BMCR_100 0x2000
[all …]
H A Dciphyreg.h44 #define CIPHY_MII_BMCR 0x00
45 #define CIPHY_BMCR_RESET 0x8000
46 #define CIPHY_BMCR_LOOP 0x4000
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
48 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
49 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
50 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
51 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
[all …]
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
H A Dnsphyterreg.h44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
45 #define PHYSTS_REL 0x8000 /* receive error latch */
46 #define PHYSTS_CIML 0x4000 /* CIM latch */
47 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
48 #define PHYSTS_DEVRDY 0x0800 /* device ready */
49 #define PHYSTS_PGRX 0x0400 /* page received */
50 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
51 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
52 #define PHYSTS_REMFAULT 0x0080 /* remote fault */
53 #define PHYSTS_JABBER 0x0040 /* jabber detect */
[all …]
H A Drgephyreg.h47 #define RGEPHY_MII_BMCR 0x00
48 #define RGEPHY_BMCR_RESET 0x8000
49 #define RGEPHY_BMCR_LOOP 0x4000
50 #define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
51 #define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
52 #define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */
53 #define RGEPHY_BMCR_ISO 0x0400 /* Isolate */
54 #define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
55 #define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
56 #define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dtdkphyreg.h39 #define VENDOR_RXCC 0x0001
40 #define VENDOR_PCSBP 0x0002
41 #define VENDOR_RVSPOL 0x0010
42 #define VENDOR_NOAPOL 0x0020
43 #define VENDOR_GPIO0DIR 0x0040
44 #define VENDOR_GPIO0DAT 0x0080
45 #define VENDOR_GPIO1DIR 0x0100
46 #define VENDOR_GPIO1DAT 0x0200
47 #define VENDOR_10BTLOOP 0x0400
48 #define VENDOR_NOSQE 0x0800
[all …]
H A Dmii.h45 #define MII_COMMAND_START 0x01
46 #define MII_COMMAND_READ 0x02
47 #define MII_COMMAND_WRITE 0x01
48 #define MII_COMMAND_ACK 0x02
50 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
51 #define BMCR_RESET 0x8000 /* reset */
52 #define BMCR_LOOP 0x4000 /* loopback */
53 #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */
54 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */
55 #define BMCR_PDOWN 0x0800 /* power down */
[all …]
H A Dxmphyreg.h42 #define XMPHY_MII_BMCR 0x00
43 #define XMPHY_BMCR_RESET 0x8000
44 #define XMPHY_BMCR_LOOP 0x4000
45 #define XMPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
46 #define XMPHY_BMCR_PDOWN 0x0800 /* Power down */
47 #define XMPHY_BMCR_ISO 0x0400 /* Isolate */
48 #define XMPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
49 #define XMPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define XMPHY_MII_BMSR 0x01
52 #define XMPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
[all …]
H A Dacphyreg.h36 #define MII_ACPHY_POL 0x10 /* Polarity int level */
39 #define MII_ACPHY_INT 0x11 /* Interrupt control/status */
40 #define AC_INT_ACOMP 0x0001 /* Autoneg complete */
41 #define AC_INT_REM_FLT 0x0002 /* Remote fault */
42 #define AC_INT_LINK_DOWN 0x0004 /* Link not OK */
43 #define AC_INT_LP_ACK 0x0008 /* FLP ack recved */
44 #define AC_INT_PD_FLT 0x0010 /* Parallel detect fault */
45 #define AC_INT_PAGE_RECV 0x0020 /* New page recved */
46 #define AC_INT_RX_ER 0x0040 /* RX_ER transitions high */
47 #define AC_INT_JAB 0x0080 /* Jabber detected */
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_urereg.h30 #define URE_CONFIG_IDX 0 /* config number 1 */
31 #define URE_IFACE_IDX 0
33 #define URE_CTL_READ 0x01
34 #define URE_CTL_WRITE 0x02
39 #define URE_BYTE_EN_DWORD 0xff
40 #define URE_BYTE_EN_WORD 0x33
41 #define URE_BYTE_EN_BYTE 0x11
42 #define URE_BYTE_EN_SIX_BYTES 0x3f
49 #define URE_PLA_IDR 0xc000
50 #define URE_PLA_RCR 0xc010
[all …]
H A Dif_axereg.h46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
H A Dyukonreg.h19 #define YUKON_GPSR 0x0000
21 #define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
22 #define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
23 #define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
24 #define YU_GPSR_LINK 0x1000 /* link status (down/up) */
25 #define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
26 #define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
27 #define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */
28 #define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */
29 #define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
[all …]
/freebsd/sys/dev/vte/
H A Dif_vtereg.h36 #define VENDORID_RDC 0x17F3
41 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
43 /* MAC control register 0 */
44 #define VTE_MCR0 0x00
45 #define MCR0_ACCPT_ERR 0x0001
46 #define MCR0_RX_ENB 0x0002
47 #define MCR0_ACCPT_RUNT 0x0004
48 #define MCR0_ACCPT_LONG_PKT 0x0008
49 #define MCR0_ACCPT_DRIBBLE 0x0010
50 #define MCR0_PROMISC 0x0020
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/sys/dev/pci/
H A Dpcireg.h53 #define PCIE_ARI_SLOTMAX 0
59 #define PCI_RID_FUNC_SHIFT 0
74 #define PCIE_ARI_RID2SLOT(rid) (0)
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
[all …]
/freebsd/sys/dev/ste/
H A Dif_stereg.h39 #define ST_VENDORID 0x13F0
40 #define ST_DEVICEID_ST201_1 0x0200
41 #define ST_DEVICEID_ST201_2 0x0201
46 #define DL_VENDORID 0x1186
47 #define DL_DEVICEID_DL10050 0x1002
56 #define STE_DMACTL 0x00
57 #define STE_TX_DMALIST_PTR 0x04
58 #define STE_TX_DMABURST_THRESH 0x08
59 #define STE_TX_DMAURG_THRESH 0x09
60 #define STE_TX_DMAPOLL_PERIOD 0x0A
[all …]
/freebsd/sys/dev/le/
H A Dlancereg.h139 #define LE_CSR0 0x0000 /* Control and status register */
140 #define LE_CSR1 0x0001 /* low address of init block */
141 #define LE_CSR2 0x0002 /* high address of init block */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
[all …]
/freebsd/sys/dev/sound/pci/
H A Dallegro_reg.h49 #define PCI_LEGACY_AUDIO_CTRL 0x40
50 #define SOUND_BLASTER_ENABLE 0x00000001
51 #define FM_SYNTHESIS_ENABLE 0x00000002
52 #define GAME_PORT_ENABLE 0x00000004
53 #define MPU401_IO_ENABLE 0x00000008
54 #define MPU401_IRQ_ENABLE 0x00000010
55 #define ALIAS_10BIT_IO 0x00000020
56 #define SB_DMA_MASK 0x000000C0
57 #define SB_DMA_0 0x00000040
58 #define SB_DMA_1 0x00000040
[all …]
/freebsd/sys/dev/agp/
H A Dagpreg.h35 #define AGP_APBASE PCIR_BAR(0)
40 #define AGP_CAPID 0x0
41 #define AGP_STATUS 0x4
42 #define AGP_COMMAND 0x8
43 #define AGP_STATUS_AGP3 0x0008
44 #define AGP_STATUS_RQ_MASK 0xff000000
45 #define AGP_COMMAND_RQ_MASK 0xff000000
46 #define AGP_STATUS_ARQSZ_MASK 0xe000
47 #define AGP_COMMAND_ARQSZ_MASK 0xe000
48 #define AGP_STATUS_CAL_MASK 0x1c00
[all …]
/freebsd/sys/sys/
H A Data.h38 #define ATA_PROTO_MASK 0x8003
39 #define ATA_PROTO_ATAPI 0x8000
40 #define ATA_PROTO_ATAPI_12 0x8000
41 #define ATA_PROTO_ATAPI_16 0x8001
42 #define ATA_PROTO_CFA 0x848a
43 #define ATA_ATAPI_TYPE_MASK 0x1f00
44 #define ATA_ATAPI_TYPE_DIRECT 0x0000 /* disk/floppy */
45 #define ATA_ATAPI_TYPE_TAPE 0x0100 /* streaming tape */
46 #define ATA_ATAPI_TYPE_CDROM 0x0500 /* CD-ROM device */
47 #define ATA_ATAPI_TYPE_OPTICAL 0x0700 /* optical disk */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]

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