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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Doxnas-nand.txt17 reg = <0x41000000 0x100000>;
21 #size-cells = <0>;
23 nand@0 {
24 reg = <0>;
30 partition@0 {
32 reg = <0x00000000 0x00e00000>;
38 reg = <0x00e00000 0x07200000>;
/freebsd/sys/dev/usb/controller/
H A Dohci.h47 #define OHCI_PAGE_SIZE 0x1000
48 #define OHCI_PAGE(x) ((x) &~ 0xfff)
49 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
50 #define OHCI_PAGE_MASK(x) ((x) & 0xfff)
52 #if ((USB_PAGE_SIZE < OHCI_ED_ALIGN) || (OHCI_ED_ALIGN == 0) || \
53 (USB_PAGE_SIZE < OHCI_TD_ALIGN) || (OHCI_TD_ALIGN == 0) || \
54 (USB_PAGE_SIZE < OHCI_ITD_ALIGN) || (OHCI_ITD_ALIGN == 0) || \
55 (USB_PAGE_SIZE < OHCI_PAGE_SIZE) || (OHCI_PAGE_SIZE == 0))
76 #define OHCI_ED_GET_FA(s) ((s) & 0x7f)
77 #define OHCI_ED_ADDRMASK 0x0000007f
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
H A Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp1021mds.dts23 reg = <0x0 0xffe05000 0x0 0x1000>;
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
27 0x1 0x0 0x0 0xf8000000 0x00008000
28 0x2 0x0 0x0 0xf8010000 0x00020000
29 0x3 0x0 0x0 0xf8020000 0x00020000>;
31 nand@0,0 {
36 reg = <0x0 0x0 0x40000>;
38 partition@0 {
41 reg = <0x0 0x00100000>;
48 reg = <0x00100000 0x00100000>;
[all …]
H A Dmpc8572ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00060000>;
77 reg = <0x07f60000 0x00020000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-extra.dtsi12 reg = <0x0 0xfc400000 0x0 0x400000>;
13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
32 reg = <0x0 0xfd5b8000 0x0 0x10000>;
37 reg = <0x0 0xfd5c0000 0x0 0x100>;
42 reg = <0x0 0xfd5cc000 0x0 0x4000>;
47 reg = <0x0 0xfd5d4000 0x0 0x4000>;
53 reg = <0x4000 0x10>;
54 #clock-cells = <0>;
58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
64 #phy-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dintel,keembay-pcie.yaml79 reg = <0x37000000 0x00001000>,
80 <0x37300000 0x00001000>,
81 <0x36e00000 0x00200000>,
82 <0x37800000 0x00000200>;
87 ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9285an.h25 #define AR9285_AN_RF2G1 0x7820
27 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
29 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
31 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
33 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
36 #define AR9285_AN_RF2G2 0x7824
38 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
41 #define AR9285_AN_RF2G3 0x7828
43 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
45 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-crs326-24g-2s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs305-1g-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs328-4c-20s-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-lenovo-ix4-300d.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
40 pinctrl-0 = <&ge0_rgmii_pins>;
48 pinctrl-0 = <&ge1_rgmii_pins>;
69 reg = <0x2e>;
74 reg = <0x50>;
[all …]
/freebsd/sys/arm/rockchip/
H A Drk32xx_machdep.c50 #define CRU_PHYSBASE 0xFF760000
51 #define CRU_SIZE 0x00010000
52 #define CRU_GLB_SRST_FST_VALUE 0x1B0
69 devmap_add_entry(0xFF000000, 0x00E00000); in rk32xx_devmap_init()
70 return (0); in rk32xx_devmap_init()
79 bus_space_map(fdtbus_bs_tag, CRU_PHYSBASE, CRU_SIZE, 0, &cru); in rk32xx_cpu_reset()
84 bus_space_write_4(fdtbus_bs_tag, cru, CRU_GLB_SRST_FST_VALUE, 0xfdb9); in rk32xx_cpu_reset()
91 * option SOCDEV_PA=0xFF600000
92 * option SOCDEV_VA=0x70000000
95 #if 0
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9001/
H A Dar9160.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
28 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2-xmc.dts47 bootargs = "earlycon=uart8250,mmio32,0x66130000";
52 reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
71 reg = <0x10>;
77 nandcs@0 {
79 reg = <0>;
88 partition@0 {
90 reg = <0x00000000 0x00280000>; /* 2.5MB */
96 reg = <0x00280000 0x00040000>; /* 0.25MB */
102 reg = <0x002c0000 0x00040000>; /* 0.25MB */
108 reg = <0x00300000 0x03d00000>; /* 61MB */
[all …]
/freebsd/contrib/elftoolchain/libpe/
H A Dpe.h75 #define IMAGE_FILE_MACHINE_UNKNOWN 0x0 /* not specified */
76 #define IMAGE_FILE_MACHINE_AM33 0x1d3 /* Matsushita AM33 */
77 #define IMAGE_FILE_MACHINE_AMD64 0x8664 /* x86-64 */
78 #define IMAGE_FILE_MACHINE_ARM 0x1c0 /* ARM LE */
79 #define IMAGE_FILE_MACHINE_ARMNT 0x1c4 /* ARMv7(or higher) Thumb */
80 #define IMAGE_FILE_MACHINE_ARM64 0xaa64 /* ARMv8 64-bit */
81 #define IMAGE_FILE_MACHINE_EBC 0xebc /* EFI byte code */
82 #define IMAGE_FILE_MACHINE_I386 0x14c /* x86 */
83 #define IMAGE_FILE_MACHINE_IA64 0x200 /* IA64 */
84 #define IMAGE_FILE_MACHINE_M32R 0x9041 /* Mitsubishi M32R LE */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sve_sme_incl.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
139 def MergeNone : MergeType<0>;
149 def EltTyInvalid : EltType<0>;
167 def MemEltTyDefault : MemEltType<0>;
179 def NoFlags : FlagType<0x00000000>;
180 def FirstEltType : FlagType<0x00000001>;
183 def EltTypeMask : FlagType<0x0000000f>;
184 def FirstMemEltType : FlagType<0x00000010>;
187 def MemEltTypeMask : FlagType<0x00000070>;
188 def FirstMergeTypeMask : FlagType<0x00000080>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x2000>,
78 <0xb0000000 0x20000>,
[all …]
/freebsd/sys/dev/my/
H A Dif_myreg.h33 #define MY_PAR0 0x0 /* physical address 0-3 */
34 #define MY_PAR1 0x04 /* physical address 4-5 */
35 #define MY_MAR0 0x08 /* multicast address 0-3 */
36 #define MY_MAR1 0x0C /* multicast address 4-7 */
37 #define MY_FAR0 0x10 /* flow-control address 0-3 */
38 #define MY_FAR1 0x14 /* flow-control address 4-5 */
39 #define MY_TCRRCR 0x18 /* receive & transmit configuration */
40 #define MY_BCR 0x1C /* bus command */
41 #define MY_TXPDR 0x20 /* transmit polling demand */
42 #define MY_RXPDR 0x24 /* receive polling demand */
[all …]

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