Lines Matching +full:0 +full:x00e00000
50 #define CRU_PHYSBASE 0xFF760000
51 #define CRU_SIZE 0x00010000
52 #define CRU_GLB_SRST_FST_VALUE 0x1B0
69 devmap_add_entry(0xFF000000, 0x00E00000); in rk32xx_devmap_init()
70 return (0); in rk32xx_devmap_init()
79 bus_space_map(fdtbus_bs_tag, CRU_PHYSBASE, CRU_SIZE, 0, &cru); in rk32xx_cpu_reset()
84 bus_space_write_4(fdtbus_bs_tag, cru, CRU_GLB_SRST_FST_VALUE, 0xfdb9); in rk32xx_cpu_reset()
91 * option SOCDEV_PA=0xFF600000
92 * option SOCDEV_VA=0x70000000
95 #if 0
101 volatile uint32_t * UART_STAT_REG = (uint32_t *)(0x7009007C);
102 volatile uint32_t * UART_TX_REG = (uint32_t *)(0x70090000);
104 while ((*UART_STAT_REG & UART_TXRDY) == 0)
122 FDT_PLATFORM_DEF2(rk32xx, rk3288, "RK3288", 0, "rockchip,rk3288", 200);
123 FDT_PLATFORM_DEF2(rk32xx, rk3288w, "RK3288W", 0, "rockchip,rk3288w", 200);