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/linux/arch/sh/kernel/cpu/sh2a/
H A Dfpu.c21 #define FPSCR_RCHG 0x00000000
32 asm volatile("sts.l fpul, @-%0\n\t" in save_fpu()
33 "sts.l fpscr, @-%0\n\t" in save_fpu()
34 "fmov.s fr15, @-%0\n\t" in save_fpu()
35 "fmov.s fr14, @-%0\n\t" in save_fpu()
36 "fmov.s fr13, @-%0\n\t" in save_fpu()
37 "fmov.s fr12, @-%0\n\t" in save_fpu()
38 "fmov.s fr11, @-%0\n\t" in save_fpu()
39 "fmov.s fr10, @-%0\n\t" in save_fpu()
40 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
H A Dmdp_reg_tdshp.h10 #define MDP_HIST_CFG_00 (0x064)
11 #define MDP_HIST_CFG_01 (0x068)
12 #define MDP_TDSHP_CTRL (0x100)
13 #define MDP_TDSHP_CFG (0x110)
14 #define MDP_TDSHP_INPUT_SIZE (0x120)
15 #define MDP_TDSHP_OUTPUT_OFFSET (0x124)
16 #define MDP_TDSHP_OUTPUT_SIZE (0x128)
17 #define MDP_LUMA_HIST_INIT (0x200)
18 #define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
19 #define MDP_CONTOUR_HIST_INIT (0x398)
[all …]
H A Dmtk-mdp3-comp.c76 0x0, BIT(0)); in init_rdma()
80 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); in init_rdma()
82 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); in init_rdma()
83 return 0; in init_rdma()
96 u32 rdma_con_mask = 0; in config_rdma_frame()
97 u32 reg = 0; in config_rdma_frame()
102 MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); in config_rdma_frame()
105 MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); in config_rdma_frame()
112 0x00030071); in config_rdma_frame()
120 0x03C8FE0F); in config_rdma_frame()
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Datmel,at91rm9200-pinctrl.yaml62 0xffffffff 0xffc00c3b # pioA
63 0xffffffff 0x7fff3ccf # pioB
64 0xffffffff 0x007fffff # pioC
69 Let's take the pioA on peripheral B whose value is 0xffc00c3b
116 'gpio@[0-9a-f]+$':
156 ranges = <0xfffff400 0xfffff400 0x600>;
160 0xffffffff 0xffc00c3b /* pioA */
161 0xffffffff 0x7fff3ccf /* pioB */
162 0xffffffff 0x007fffff /* pioC */
166 pinctrl_dbgu: dbgu-0 {
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux/arch/mips/math-emu/
H A Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/drivers/regulator/
H A Dqcom_rpm-regulator.c67 .mV = { 0, 0x00000FFF, 0 },
68 .ip = { 0, 0x00FFF000, 12 },
69 .fm = { 0, 0x03000000, 24 },
70 .pc = { 0, 0x3C000000, 26 },
71 .pf = { 0, 0xC0000000, 30 },
72 .pd = { 1, 0x00000001, 0 },
73 .ia = { 1, 0x00001FFE, 1 },
78 .mV = { 0, 0x00000FFF, 0 },
79 .ip = { 0, 0x00FFF000, 12 },
80 .fm = { 0, 0x03000000, 24 },
[all …]
/linux/arch/powerpc/include/asm/
H A Dcode-patching.h17 * "b" == create_branch(addr, target, 0);
22 #define BRANCH_SET_LINK 0x1
23 #define BRANCH_ABSOLUTE 0x2
28 * 0 6 30 31
32 * Where AA = 0 and LK = 0
35 * by: imm32 = SignExtend(LI:'0b00', 32);
38 * (0x007fffff << 2) = 0x01fffffc = 0x1fffffc
40 * (0xff800000 << 2) = 0xfe000000 = -0x2000000
44 return (offset >= -0x2000000 && offset <= 0x1fffffc && !(offset & 0x3)); in is_offset_in_branch_range()
49 return offset >= -0x8000 && offset <= 0x7fff && !(offset & 0x3); in is_offset_in_cond_branch_range()
[all …]
/linux/drivers/dio/
H A Ddio.c41 { .name = "DIO mem", .start = 0x00600000, .end = 0x007fffff },
43 { .name = "DIO-II mem", .start = 0x01000000, .end = 0x1fffffff }
98 for (i = 0; i < ARRAY_SIZE(names); i++) in dio_getname()
107 static char dio_no_name[] = { 0 };
126 for (scode = 0; scode < DIO_SCMAX; scode++) { in dio_find()
179 return 0; in dio_init()
194 for (i = 0; i < dio_bus.num_resources; i++) in dio_init()
198 for (scode = 0; scode < DIO_SCMAX; ++scode) { in dio_init()
199 u_char prid, secid = 0; /* primary, secondary ID bytes */ in dio_init()
269 return 0; in dio_init()
[all …]
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h32 #define XAE_OPTION_PROMISC BIT(0)
75 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
76 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
77 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
78 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
80 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
81 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
82 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
83 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
85 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
[all …]
/linux/arch/arm/probes/kprobes/
H A Dopt-arm.c38 " sub sp, sp, #0xff\n"
42 " add r3, sp, #0xff\n"
51 * SP % 8 != 0 (SP % 4 == 0 should be ensured),
80 "1: .long 0\n"
83 "2: .long 0\n"
117 * kprobe in the address range. So always return 0.
121 return 0; in arch_check_optimized_kprobe()
124 /* Caller must ensure addr & 3 == 0 */
127 if (kp->ainsn.stack_space < 0) in can_optimize()
128 return 0; in can_optimize()
[all …]
/linux/drivers/hwmon/
H A Dlochnagar-hwmon.c51 LN2_CURR = 0,
72 u64 man = data & 0x007FFFFF; in float_to_long()
73 int exp = ((data & 0x7F800000) >> 23) - 127 - 23; in float_to_long()
74 bool negative = data & 0x80000000; in float_to_long()
81 else if (exp < 0) in float_to_long()
99 if (ret < 0) in do_measurement()
103 if (ret < 0) in do_measurement()
108 if (ret < 0) in do_measurement()
114 if (ret < 0) in do_measurement()
119 if (ret < 0) in do_measurement()
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/drivers/net/ethernet/ni/
H A Dnixge.c25 #define XAXIDMA_TX_CR_OFFSET 0x00 /* Channel control */
26 #define XAXIDMA_TX_SR_OFFSET 0x04 /* Status */
27 #define XAXIDMA_TX_CDESC_OFFSET 0x08 /* Current descriptor pointer */
28 #define XAXIDMA_TX_TDESC_OFFSET 0x10 /* Tail descriptor pointer */
30 #define XAXIDMA_RX_CR_OFFSET 0x30 /* Channel control */
31 #define XAXIDMA_RX_SR_OFFSET 0x34 /* Status */
32 #define XAXIDMA_RX_CDESC_OFFSET 0x38 /* Current descriptor pointer */
33 #define XAXIDMA_RX_TDESC_OFFSET 0x40 /* Tail descriptor pointer */
35 #define XAXIDMA_CR_RUNSTOP_MASK 0x1 /* Start/stop DMA channel */
36 #define XAXIDMA_CR_RESET_MASK 0x4 /* Reset DMA engine */
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dfpu.c22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
54 "fmov.s fr11, @-%0\n\t" in save_fpu()
55 "fmov.s fr10, @-%0\n\t" in save_fpu()
56 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
H A Dsoftfloat.c116 return a & LIT64(0x000FFFFFFFFFFFFF); in extractFloat64Frac()
126 return (a >> 52) & 0x7FF; in extractFloat64Exp()
131 return (a >> 23) & 0xFF; in extractFloat32Exp()
141 return a & 0x007FFFFF; in extractFloat32Frac()
153 if (count == 0) { in shift64RightJamming()
156 z = (a >> count) | ((a << ((-count) & 63)) != 0); in shift64RightJamming()
158 z = (a != 0); in shift64RightJamming()
174 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, in countLeadingZeros32()
175 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, in countLeadingZeros32()
176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, in countLeadingZeros32()
[all …]
/linux/arch/m68k/68000/
H A Dhead.S24 #define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)-(CONFIG_MEMORY_RESERVE*0x100000)
51 .long 0
53 .long 0
55 .long 0
57 .long 0
69 .byte 0x4e, 0xfa, 0x00, 0x0a /* bra opcode (jmp 10 bytes) */
73 moveq #0, %d0
74 movew %d0, 0xfffff618 /* Watchdog off */
75 movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
78 movew #0x2700, %sr /* disable all interrupts */
[all …]
/linux/arch/parisc/math-emu/
H A Dsgl_float.h38 #define Sgl_clear_signexponent(srcdst) Sall(srcdst) &= 0x007fffff
67 #define Sgl_isone_sign(sgl_value) (Is_ssign(sgl_value)!=0)
69 (Is_shiddenoverflow(sgl_value)!=0)
70 #define Sgl_isone_lowmantissa(sgl_value) (Is_slow(sgl_value)!=0)
71 #define Sgl_isone_signaling(sgl_value) (Is_ssignaling(sgl_value)!=0)
72 #define Sgl_is_signalingnan(sgl_value) (Ssignalingnan(sgl_value)==0x1ff)
73 #define Sgl_isnotzero(sgl_value) (Sall(sgl_value)!=0)
75 (Shiddenhigh7mantissa(sgl_value)!=0)
76 #define Sgl_isnotzero_low4(sgl_value) (Slow4(sgl_value)!=0)
77 #define Sgl_isnotzero_exponent(sgl_value) (Sexponent(sgl_value)!=0)
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9260.dtsi41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA0_HYP_DEC_REG_START 0x5880
59 #define SDMA0_HYP_DEC_REG_END 0x5893
60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
[all …]
/linux/sound/pci/asihpi/
H A Dhpi6205.c56 #define C6205_HSR_INTSRC 0x01
57 #define C6205_HSR_INTAVAL 0x02
58 #define C6205_HSR_INTAM 0x04
59 #define C6205_HSR_CFGERR 0x08
60 #define C6205_HSR_EEREAD 0x10
62 #define C6205_HDCR_WARMRESET 0x01
63 #define C6205_HDCR_DSPINT 0x02
64 #define C6205_HDCR_PCIBOOT 0x04
67 #define C6205_DSPP_MAP1 0x400
71 * of DSP memory mapped registers (starting at 0x01800000).
[all …]
/linux/sound/pci/lx6464es/
H A Dlx_core.c23 0,
24 0x400,
25 0x401,
26 0x402,
27 0x403,
28 0x404,
29 0x405,
30 0x406,
31 0x407,
32 0x408,
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dsiena.c53 FRF_CZ_TC_TIMER_VAL, 0); in siena_push_irq_moderation()
61 if (efx->fc_disable++ == 0) in efx_siena_prepare_flush()
67 if (--efx->fc_disable == 0) in siena_finish_flush()
73 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
75 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
77 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
79 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
81 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
83 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
85 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
[all …]

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