1*fbb6c848SEzequiel Garcia /* SPDX-License-Identifier: GPL-2.0 */ 2*fbb6c848SEzequiel Garcia /* 3*fbb6c848SEzequiel Garcia * Hantro VPU codec driver 4*fbb6c848SEzequiel Garcia * 5*fbb6c848SEzequiel Garcia * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 6*fbb6c848SEzequiel Garcia * Alpha Lin <alpha.lin@rock-chips.com> 7*fbb6c848SEzequiel Garcia */ 8*fbb6c848SEzequiel Garcia 9*fbb6c848SEzequiel Garcia #ifndef ROCKCHIP_VPU2_REGS_H_ 10*fbb6c848SEzequiel Garcia #define ROCKCHIP_VPU2_REGS_H_ 11*fbb6c848SEzequiel Garcia 12*fbb6c848SEzequiel Garcia /* Encoder registers. */ 13*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24)) 14*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) 15*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) 16*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24)) 17*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) 18*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) 19*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24)) 20*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) 21*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) 22*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24)) 23*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) 24*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) 25*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) 26*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_5TH(i) (0x010 + ((i) * 0x24)) 27*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) 28*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) 29*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_ZB_AC_Y1(x) (((x) & 0x1ff) << 0) 30*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_6TH(i) (0x014 + ((i) * 0x24)) 31*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_DC_CHR(x) (((x) & 0xff) << 16) 32*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_DC_Y2(x) (((x) & 0xff) << 8) 33*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_DC_Y1(x) (((x) & 0xff) << 0) 34*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_7TH(i) (0x018 + ((i) * 0x24)) 35*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_AC_CHR(x) (((x) & 0xff) << 16) 36*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_AC_Y2(x) (((x) & 0xff) << 8) 37*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_RND_AC_Y1(x) (((x) & 0xff) << 0) 38*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_8TH(i) (0x01c + ((i) * 0x24)) 39*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG_FILTER_LEVEL(x) (((x) & 0x3f) << 25) 40*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_DC_CHR(x) (((x) & 0xff) << 17) 41*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_DC_Y2(x) (((x) & 0x1ff) << 8) 42*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_DC_Y1(x) (((x) & 0xff) << 0) 43*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_QUT_9TH(i) (0x020 + ((i) * 0x24)) 44*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_AC_CHR(x) (((x) & 0x1ff) << 18) 45*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_AC_Y2(x) (((x) & 0x1ff) << 9) 46*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DEQUT_AC_Y1(x) (((x) & 0x1ff) << 0) 47*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_VP8_SEG_MAP 0x06c 48*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_4X4_PENALTY(i) (0x070 + ((i) * 0x4)) 49*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x) (((x) & 0xfff) << 0) 50*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x) (((x) & 0xfff) << 16) 51*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_16X16_PENALTY(i) (0x084 + ((i) * 0x4)) 52*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x) (((x) & 0xfff) << 0) 53*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x) (((x) & 0xfff) << 16) 54*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_CONTROL 0x0a0 55*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x) (((x) & 0x1f) << 24) 56*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x) (((x) & 0x7f) << 16) 57*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_INTER_TYPE_BIT_COST(x) (((x) & 0xfff) << 0) 58*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_REF_FRAME_VAL 0x0a4 59*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_COEF_DMV_PENALTY(x) (((x) & 0xfff) << 16) 60*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_REF_FRAME(x) (((x) & 0xfff) << 0) 61*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LOOP_FILTER_REF_DELTA 0x0a8 62*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x) (((x) & 0x7f) << 16) 63*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x) (((x) & 0x7f) << 8) 64*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x) (((x) & 0x7f) << 0) 65*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA 0x0ac 66*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x) (((x) & 0x7f) << 16) 67*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x) (((x) & 0x7f) << 8) 68*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x) (((x) & 0x7f) << 0) 69*fbb6c848SEzequiel Garcia #define VEPU_REG_JPEG_LUMA_QUAT(i) (0x000 + ((i) * 0x4)) 70*fbb6c848SEzequiel Garcia #define VEPU_REG_JPEG_CHROMA_QUAT(i) (0x040 + ((i) * 0x4)) 71*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_SLICE_BITMAP(i) (0x0b0 + ((i) * 0x4)) 72*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_VP8_DCT_PART(i) (0x0b0 + ((i) * 0x4)) 73*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_AREA_CTRL 0x0b8 74*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 24) 75*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 16) 76*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 8) 77*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 0) 78*fbb6c848SEzequiel Garcia #define VEPU_REG_CIR_INTRA_CTRL 0x0bc 79*fbb6c848SEzequiel Garcia #define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16) 80*fbb6c848SEzequiel Garcia #define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0) 81*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_IN_PLANE_0 0x0c0 82*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_IN_PLANE_1 0x0c4 83*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_IN_PLANE_2 0x0c8 84*fbb6c848SEzequiel Garcia #define VEPU_REG_STR_HDR_REM_MSB 0x0cc 85*fbb6c848SEzequiel Garcia #define VEPU_REG_STR_HDR_REM_LSB 0x0d0 86*fbb6c848SEzequiel Garcia #define VEPU_REG_STR_BUF_LIMIT 0x0d4 87*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL 0x0d8 88*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 24) 89*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 16) 90*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8) 91*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_INCREMENT_MODE(x) (((x) & 0x01) << 2) 92*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_BIRST_DISCARD(x) (((x) & 0x01) << 1) 93*fbb6c848SEzequiel Garcia #define VEPU_REG_AXI_CTRL_BIRST_DISABLE BIT(0) 94*fbb6c848SEzequiel Garcia #define VEPU_QP_ADJUST_MAD_DELTA_ROI 0x0dc 95*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 12) 96*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 8) 97*fbb6c848SEzequiel Garcia #define VEPU_REG_MAD_QP_ADJUSTMENT (((x) & 0xf) << 0) 98*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_REF_LUMA 0x0e0 99*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_REF_CHROMA 0x0e4 100*fbb6c848SEzequiel Garcia #define VEPU_REG_QP_SUM_DIV2 0x0e8 101*fbb6c848SEzequiel Garcia #define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2) 102*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_CTRL0 0x0ec 103*fbb6c848SEzequiel Garcia #define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(28) 104*fbb6c848SEzequiel Garcia #define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 24) 105*fbb6c848SEzequiel Garcia #define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 21) 106*fbb6c848SEzequiel Garcia #define VEPU_REG_ENTROPY_CODING_MODE BIT(20) 107*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_TRANS8X8_MODE BIT(17) 108*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_INTER4X4_MODE BIT(16) 109*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_STREAM_MODE BIT(15) 110*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 8) 111*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_OVER_FILL_STRM_OFFSET 0x0f0 112*fbb6c848SEzequiel Garcia #define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 16) 113*fbb6c848SEzequiel Garcia #define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 8) 114*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 4) 115*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 0) 116*fbb6c848SEzequiel Garcia #define VEPU_REG_INPUT_LUMA_INFO 0x0f4 117*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 20) 118*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 16) 119*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 0) 120*fbb6c848SEzequiel Garcia #define VEPU_REG_RLC_SUM 0x0f8 121*fbb6c848SEzequiel Garcia #define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4) 122*fbb6c848SEzequiel Garcia #define VEPU_REG_SPLIT_PENALTY_4X4 0x0f8 123*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SPLIT_PENALTY_4X4 (((x) & 0x1ff) << 19) 124*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_REC_LUMA 0x0fc 125*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_REC_CHROMA 0x100 126*fbb6c848SEzequiel Garcia #define VEPU_REG_CHECKPOINT(i) (0x104 + ((i) * 0x4)) 127*fbb6c848SEzequiel Garcia #define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) 128*fbb6c848SEzequiel Garcia #define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) 129*fbb6c848SEzequiel Garcia #define VEPU_REG_CHECKPOINT_RESULT(x) \ 130*fbb6c848SEzequiel Garcia ((((x) >> (16 - 16 * ((i) & 1))) & 0xffff) * 32) 131*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_AC_Y1 0x104 132*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_AC_Y1(x) (((x) & 0xff) << 23) 133*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y1(x) (((x) & 0x1ff) << 14) 134*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_AC_Y1(x) (((x) & 0x3fff) << 0) 135*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_DC_Y2 0x108 136*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_DC_Y2(x) (((x) & 0xff) << 23) 137*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y2(x) (((x) & 0x1ff) << 14) 138*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_DC_Y2(x) (((x) & 0x3fff) << 0) 139*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_AC_Y2 0x10c 140*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_AC_Y2(x) (((x) & 0xff) << 23) 141*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y2(x) (((x) & 0x1ff) << 14) 142*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) 143*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_DC_CHR 0x110 144*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_DC_CHR(x) (((x) & 0xff) << 23) 145*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_DC_CHR(x) (((x) & 0x1ff) << 14) 146*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) 147*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_AC_CHR 0x114 148*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_AC_CHR(x) (((x) & 0xff) << 23) 149*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_AC_CHR(x) (((x) & 0x1ff) << 14) 150*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_AC_CHR(x) (((x) & 0x3fff) << 0) 151*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_DQUT 0x118 152*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_MV_REF_IDX1(x) (((x) & 0x03) << 26) 153*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_DC_Y2(x) (((x) & 0x1ff) << 17) 154*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_AC_Y1(x) (((x) & 0x1ff) << 8) 155*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_DC_Y1(x) (((x) & 0xff) << 0) 156*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_WORD_ERR(i) (0x118 + ((i) * 0x4)) 157*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) 158*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) 159*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_DQUT_1 0x11c 160*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEGMENT_MAP_UPDATE BIT(30) 161*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEGMENT_EN BIT(29) 162*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_MV_REF_IDX2_EN BIT(28) 163*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_MV_REF_IDX2(x) (((x) & 0x03) << 26) 164*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_AC_CHR(x) (((x) & 0x1ff) << 17) 165*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_DC_CHR(x) (((x) & 0xff) << 9) 166*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_DQUT_AC_Y2(x) (((x) & 0x1ff) << 0) 167*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_BOOL_ENC_VALUE 0x120 168*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP 0x124 169*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) 170*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) 171*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) 172*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) 173*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) 174*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) 175*fbb6c848SEzequiel Garcia #define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) 176*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_ENC_CTRL2 0x124 177*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2(x) (((x) & 0xff) << 24) 178*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_FILTER_SHARPNESS(x) (((x) & 0x07) << 21) 179*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_FILTER_LEVEL(x) (((x) & 0x3f) << 15) 180*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_DCT_PARTITION_CNT(x) (((x) & 0x03) << 13) 181*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_BOOL_ENC_VALUE_BITS(x) (((x) & 0x1f) << 8) 182*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_BOOL_ENC_RANGE(x) (((x) & 0xff) << 0) 183*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_CTRL1 0x128 184*fbb6c848SEzequiel Garcia #define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 24) 185*fbb6c848SEzequiel Garcia #define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16) 186*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 4) 187*fbb6c848SEzequiel Garcia #define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 2) 188*fbb6c848SEzequiel Garcia #define VEPU_REG_SIZE_TABLE_PRESENT BIT(0) 189*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_INTER_MODE 0x12c 190*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 16) 191*fbb6c848SEzequiel Garcia #define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0) 192*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_CTRL2 0x130 193*fbb6c848SEzequiel Garcia #define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26) 194*fbb6c848SEzequiel Garcia #define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22) 195*fbb6c848SEzequiel Garcia #define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18) 196*fbb6c848SEzequiel Garcia #define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13) 197*fbb6c848SEzequiel Garcia #define VEPU_REG_FILTER_DISABLE BIT(5) 198*fbb6c848SEzequiel Garcia #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) 199*fbb6c848SEzequiel Garcia #define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0) 200*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_OUTPUT_STREAM 0x134 201*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_OUTPUT_CTRL 0x138 202*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_NEXT_PIC 0x13c 203*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_MV_OUT 0x140 204*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_CABAC_TBL 0x144 205*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI1 0x148 206*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 24) 207*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 16) 208*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 8) 209*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 0) 210*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI2 0x14c 211*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 24) 212*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 16) 213*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 8) 214*fbb6c848SEzequiel Garcia #define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 0) 215*fbb6c848SEzequiel Garcia #define VEPU_REG_STABLE_MATRIX(i) (0x150 + ((i) * 0x4)) 216*fbb6c848SEzequiel Garcia #define VEPU_REG_STABLE_MOTION_SUM 0x174 217*fbb6c848SEzequiel Garcia #define VEPU_REG_STABILIZATION_OUTPUT 0x178 218*fbb6c848SEzequiel Garcia #define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 8) 219*fbb6c848SEzequiel Garcia #define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 6) 220*fbb6c848SEzequiel Garcia #define VEPU_REG_STABLE_HOR_GMV(x) (((x) & 0x3f) << 0) 221*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEF1 0x17c 222*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16) 223*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0) 224*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEF2 0x180 225*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16) 226*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0) 227*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEF3 0x184 228*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0) 229*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB_MASK_MSB 0x188 230*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 16) 231*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 8) 232*fbb6c848SEzequiel Garcia #define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 0) 233*fbb6c848SEzequiel Garcia #define VEPU_REG_MV_PENALTY 0x18c 234*fbb6c848SEzequiel Garcia #define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 21) 235*fbb6c848SEzequiel Garcia #define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 11) 236*fbb6c848SEzequiel Garcia #define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 1) 237*fbb6c848SEzequiel Garcia #define VEPU_REG_SPLIT_MV_MODE_EN BIT(0) 238*fbb6c848SEzequiel Garcia #define VEPU_REG_QP_VAL 0x190 239*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26) 240*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20) 241*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14) 242*fbb6c848SEzequiel Garcia #define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0) 243*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUANT_DC_Y1 0x190 244*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_RND_DC_Y1(x) (((x) & 0xff) << 23) 245*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y1(x) (((x) & 0x1ff) << 14) 246*fbb6c848SEzequiel Garcia #define VEPU_REG_VP8_SEG0_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) 247*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_RELATE 0x198 248*fbb6c848SEzequiel Garcia #define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 20) 249*fbb6c848SEzequiel Garcia #define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 11) 250*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 8) 251*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(7) 252*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 4) 253*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 1) 254*fbb6c848SEzequiel Garcia #define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(0) 255*fbb6c848SEzequiel Garcia #define VEPU_REG_ENCODE_START 0x19c 256*fbb6c848SEzequiel Garcia #define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 20) 257*fbb6c848SEzequiel Garcia #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) 258*fbb6c848SEzequiel Garcia #define VEPU_REG_FRAME_TYPE_INTER (0x0 << 6) 259*fbb6c848SEzequiel Garcia #define VEPU_REG_FRAME_TYPE_INTRA (0x1 << 6) 260*fbb6c848SEzequiel Garcia #define VEPU_REG_FRAME_TYPE_MVCINTER (0x2 << 6) 261*fbb6c848SEzequiel Garcia #define VEPU_REG_ENCODE_FORMAT_JPEG (0x2 << 4) 262*fbb6c848SEzequiel Garcia #define VEPU_REG_ENCODE_FORMAT_H264 (0x3 << 4) 263*fbb6c848SEzequiel Garcia #define VEPU_REG_ENCODE_ENABLE BIT(0) 264*fbb6c848SEzequiel Garcia #define VEPU_REG_MB_CTRL 0x1a0 265*fbb6c848SEzequiel Garcia #define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 16) 266*fbb6c848SEzequiel Garcia #define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 0) 267*fbb6c848SEzequiel Garcia #define VEPU_REG_DATA_ENDIAN 0x1a4 268*fbb6c848SEzequiel Garcia #define VEPU_REG_INPUT_SWAP8 BIT(31) 269*fbb6c848SEzequiel Garcia #define VEPU_REG_INPUT_SWAP16 BIT(30) 270*fbb6c848SEzequiel Garcia #define VEPU_REG_INPUT_SWAP32 BIT(29) 271*fbb6c848SEzequiel Garcia #define VEPU_REG_OUTPUT_SWAP8 BIT(28) 272*fbb6c848SEzequiel Garcia #define VEPU_REG_OUTPUT_SWAP16 BIT(27) 273*fbb6c848SEzequiel Garcia #define VEPU_REG_OUTPUT_SWAP32 BIT(26) 274*fbb6c848SEzequiel Garcia #define VEPU_REG_TEST_IRQ BIT(24) 275*fbb6c848SEzequiel Garcia #define VEPU_REG_TEST_COUNTER(x) (((x) & 0xf) << 20) 276*fbb6c848SEzequiel Garcia #define VEPU_REG_TEST_REG BIT(19) 277*fbb6c848SEzequiel Garcia #define VEPU_REG_TEST_MEMORY BIT(18) 278*fbb6c848SEzequiel Garcia #define VEPU_REG_TEST_LEN(x) (((x) & 0x3ffff) << 0) 279*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_CTRL3 0x1a8 280*fbb6c848SEzequiel Garcia #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) 281*fbb6c848SEzequiel Garcia #define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16) 282*fbb6c848SEzequiel Garcia #define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0) 283*fbb6c848SEzequiel Garcia #define VEPU_REG_ENC_CTRL4 0x1ac 284*fbb6c848SEzequiel Garcia #define VEPU_REG_MV_PENALTY_16X8_8X16(x) (((x) & 0x3ff) << 20) 285*fbb6c848SEzequiel Garcia #define VEPU_REG_MV_PENALTY_8X8(x) (((x) & 0x3ff) << 10) 286*fbb6c848SEzequiel Garcia #define VEPU_REG_MV_PENALTY_8X4_4X8(x) (((x) & 0x3ff) << 0) 287*fbb6c848SEzequiel Garcia #define VEPU_REG_ADDR_VP8_PROB_CNT 0x1b0 288*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT 0x1b4 289*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_NON BIT(28) 290*fbb6c848SEzequiel Garcia #define VEPU_REG_MV_WRITE_EN BIT(24) 291*fbb6c848SEzequiel Garcia #define VEPU_REG_RECON_WRITE_DIS BIT(20) 292*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(16) 293*fbb6c848SEzequiel Garcia #define VEPU_REG_CLK_GATING_EN BIT(12) 294*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(10) 295*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_RESET BIT(9) 296*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_DIS_BIT BIT(8) 297*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_TIMEOUT BIT(6) 298*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5) 299*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_BUS_ERROR BIT(4) 300*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_FUSE BIT(3) 301*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_SLICE_READY BIT(2) 302*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_FRAME_READY BIT(1) 303*fbb6c848SEzequiel Garcia #define VEPU_REG_INTERRUPT_BIT BIT(0) 304*fbb6c848SEzequiel Garcia #define VEPU_REG_DMV_PENALTY_TBL(i) (0x1E0 + ((i) * 0x4)) 305*fbb6c848SEzequiel Garcia #define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) 306*fbb6c848SEzequiel Garcia #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i) (0x260 + ((i) * 0x4)) 307*fbb6c848SEzequiel Garcia #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) 308*fbb6c848SEzequiel Garcia 309*fbb6c848SEzequiel Garcia /* vpu decoder register */ 310*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0 0x0c8 // 50 311*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 25) 312*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 13) 313*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(12) 314*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(11) 315*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(10) 316*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(9) 317*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(8) 318*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(7) 319*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 1) 320*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) 321*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(0) 322*fbb6c848SEzequiel Garcia #define VDPU_REG_STREAM_LEN 0x0cc 323*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) 324*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_STREAM_LEN_HI BIT(24) 325*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) 326*fbb6c848SEzequiel Garcia #define VDPU_REG_ERROR_CONCEALMENT 0x0d0 327*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 17) 328*fbb6c848SEzequiel Garcia #define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 8) 329*fbb6c848SEzequiel Garcia #define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 0) 330*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_FORMAT 0x0d4 331*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 0) 332*fbb6c848SEzequiel Garcia #define VDPU_REG_DATA_ENDIAN 0x0d8 333*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(5) 334*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(4) 335*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(3) 336*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(2) 337*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(1) 338*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(0) 339*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT 0x0dc 340*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(13) 341*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(12) 342*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(10) 343*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(9) 344*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(8) 345*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(6) 346*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(5) 347*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(4) 348*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(1) 349*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_IRQ BIT(0) 350*fbb6c848SEzequiel Garcia #define VDPU_REG_AXI_CTRL 0x0e0 351*fbb6c848SEzequiel Garcia #define VDPU_REG_AXI_DEC_SEL BIT(23) 352*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(22) 353*fbb6c848SEzequiel Garcia #define VDPU_REG_PARAL_BUS_E(x) BIT(21) 354*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 16) 355*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 8) 356*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 0) 357*fbb6c848SEzequiel Garcia #define VDPU_REG_EN_FLAGS 0x0e4 358*fbb6c848SEzequiel Garcia #define VDPU_REG_AHB_HLOCK_E BIT(31) 359*fbb6c848SEzequiel Garcia #define VDPU_REG_CACHE_E BIT(29) 360*fbb6c848SEzequiel Garcia #define VDPU_REG_PREFETCH_SINGLE_CHANNEL_E BIT(28) 361*fbb6c848SEzequiel Garcia #define VDPU_REG_INTRA_3_CYCLE_ENHANCE BIT(27) 362*fbb6c848SEzequiel Garcia #define VDPU_REG_INTRA_DOUBLE_SPEED BIT(26) 363*fbb6c848SEzequiel Garcia #define VDPU_REG_INTER_DOUBLE_SPEED BIT(25) 364*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(22) 365*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(21) 366*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(20) 367*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(19) 368*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(18) 369*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(17) 370*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(16) 371*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(15) 372*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(14) 373*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(13) 374*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(12) 375*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(11) 376*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(10) 377*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(9) 378*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(8) 379*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(7) 380*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(6) 381*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(5) 382*fbb6c848SEzequiel Garcia #define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(4) 383*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(2) 384*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(1) 385*fbb6c848SEzequiel Garcia #define VDPU_REG_INTERRUPT_DEC_E BIT(0) 386*fbb6c848SEzequiel Garcia #define VDPU_REG_SOFT_RESET 0x0e8 387*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT 0x0ec 388*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) 389*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) 390*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) 391*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDITIONAL_CHROMA_ADDRESS 0x0f0 392*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDR_QTABLE 0x0f4 393*fbb6c848SEzequiel Garcia #define VDPU_REG_DIRECT_MV_ADDR 0x0f8 394*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDR_DST 0x0fc 395*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDR_STR 0x100 396*fbb6c848SEzequiel Garcia #define VDPU_REG_REFBUF_RELATED 0x104 397*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC(i) (0x128 + ((i) * 0x4)) 398*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) 399*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) 400*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 401*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 402*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 403*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 404*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC(i) (0x130 + ((i) * 0x4)) 405*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16) 406*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0) 407*fbb6c848SEzequiel Garcia #define VDPU_REG_H264_ADDR_REF(i) (0x150 + ((i) * 0x4)) 408*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDR_REF_FIELD_E BIT(1) 409*fbb6c848SEzequiel Garcia #define VDPU_REG_ADDR_REF_TOPC_E BIT(0) 410*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST0 0x190 411*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5(x) (((x) & 0x1f) << 25) 412*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4(x) (((x) & 0x1f) << 20) 413*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 414*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 415*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 416*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 417*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST1 0x194 418*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11(x) (((x) & 0x1f) << 25) 419*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10(x) (((x) & 0x1f) << 20) 420*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9(x) (((x) & 0x1f) << 15) 421*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8(x) (((x) & 0x1f) << 10) 422*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7(x) (((x) & 0x1f) << 5) 423*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6(x) (((x) & 0x1f) << 0) 424*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST2 0x198 425*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 15) 426*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14(x) (((x) & 0x1f) << 10) 427*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13(x) (((x) & 0x1f) << 5) 428*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12(x) (((x) & 0x1f) << 0) 429*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST3 0x19c 430*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5(x) (((x) & 0x1f) << 25) 431*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4(x) (((x) & 0x1f) << 20) 432*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3(x) (((x) & 0x1f) << 15) 433*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 10) 434*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 5) 435*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 0) 436*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST4 0x1a0 437*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11(x) (((x) & 0x1f) << 25) 438*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10(x) (((x) & 0x1f) << 20) 439*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9(x) (((x) & 0x1f) << 15) 440*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8(x) (((x) & 0x1f) << 10) 441*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7(x) (((x) & 0x1f) << 5) 442*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6(x) (((x) & 0x1f) << 0) 443*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST5 0x1a4 444*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 15) 445*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14(x) (((x) & 0x1f) << 10) 446*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13(x) (((x) & 0x1f) << 5) 447*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12(x) (((x) & 0x1f) << 0) 448*fbb6c848SEzequiel Garcia #define VDPU_REG_INITIAL_REF_PIC_LIST6 0x1a8 449*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 450*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 451*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 452*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 453*fbb6c848SEzequiel Garcia #define VDPU_REG_LT_REF 0x1ac 454*fbb6c848SEzequiel Garcia #define VDPU_REG_VALID_REF 0x1b0 455*fbb6c848SEzequiel Garcia #define VDPU_REG_H264_PIC_MB_SIZE 0x1b8 456*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 22) 457*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 17) 458*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 9) 459*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 0) 460*fbb6c848SEzequiel Garcia #define VDPU_REG_H264_CTRL 0x1bc 461*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 16) 462*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) 463*fbb6c848SEzequiel Garcia #define VDPU_REG_CURRENT_FRAME 0x1c0 464*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(31) 465*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(30) 466*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16) 467*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0) 468*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_FRAME 0x1c4 469*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 16) 470*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0) 471*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6 0x1c8 472*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) 473*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) 474*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) 475*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0) 476*fbb6c848SEzequiel Garcia #define VDPU_REG_ENABLE_FLAG 0x1cc 477*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(8) 478*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(7) 479*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(6) 480*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_CABAC_E BIT(5) 481*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(4) 482*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(3) 483*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(2) 484*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(1) 485*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) 486*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_PIC_MB_SIZE 0x1e0 487*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) 488*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) 489*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) 490*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) 491*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) 492*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) 493*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_DCT_START_BIT 0x1e4 494*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26) 495*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20) 496*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) 497*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) 498*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_CTRL0 0x1e8 499*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) 500*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18) 501*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8) 502*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) 503*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_DATA_VAL 0x1f0 504*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) 505*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) 506*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT7 0x1f4 507*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1(x) (((x) & 0x3ff) << 22) 508*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2(x) (((x) & 0x3ff) << 12) 509*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3(x) (((x) & 0x3ff) << 2) 510*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT8 0x1f8 511*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0(x) (((x) & 0x3ff) << 22) 512*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1(x) (((x) & 0x3ff) << 12) 513*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2(x) (((x) & 0x3ff) << 2) 514*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT9 0x1fc 515*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3(x) (((x) & 0x3ff) << 22) 516*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0(x) (((x) & 0x3ff) << 12) 517*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1(x) (((x) & 0x3ff) << 2) 518*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT10 0x200 519*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2(x) (((x) & 0x3ff) << 22) 520*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3(x) (((x) & 0x3ff) << 12) 521*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10) 522*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8) 523*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6) 524*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4) 525*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2) 526*fbb6c848SEzequiel Garcia #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0) 527*fbb6c848SEzequiel Garcia #define VDPU_REG_FILTER_LEVEL 0x204 528*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18) 529*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12) 530*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6) 531*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0) 532*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_QUANTER0 0x208 533*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27) 534*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) 535*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) 536*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) 537*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_ADDR_REF0 0x20c 538*fbb6c848SEzequiel Garcia #define VDPU_REG_FILTER_MB_ADJ 0x210 539*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) 540*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) 541*fbb6c848SEzequiel Garcia #define VDPU_REG_FILT_MB_ADJ_0(x) (((x) & 0x7f) << 21) 542*fbb6c848SEzequiel Garcia #define VDPU_REG_FILT_MB_ADJ_1(x) (((x) & 0x7f) << 14) 543*fbb6c848SEzequiel Garcia #define VDPU_REG_FILT_MB_ADJ_2(x) (((x) & 0x7f) << 7) 544*fbb6c848SEzequiel Garcia #define VDPU_REG_FILT_MB_ADJ_3(x) (((x) & 0x7f) << 0) 545*fbb6c848SEzequiel Garcia #define VDPU_REG_FILTER_REF_ADJ 0x214 546*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_ADJ_0(x) (((x) & 0x7f) << 21) 547*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_ADJ_1(x) (((x) & 0x7f) << 14) 548*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_ADJ_2(x) (((x) & 0x7f) << 7) 549*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_ADJ_3(x) (((x) & 0x7f) << 0) 550*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_ADDR_REF2_5(i) (0x218 + ((i) * 0x4)) 551*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_GREF_SIGN_BIAS BIT(0) 552*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_AREF_SIGN_BIAS BIT(0) 553*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_DCT_BASE(i) (0x230 + ((i) * 0x4)) 554*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_ADDR_CTRL_PART 0x244 555*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_ADDR_REF1 0x250 556*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_SEGMENT_VAL 0x254 557*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) 558*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) 559*fbb6c848SEzequiel Garcia #define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) 560*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_DCT_START_BIT2 0x258 561*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24) 562*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18) 563*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) 564*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) 565*fbb6c848SEzequiel Garcia #define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) 566*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_QUANTER1 0x25c 567*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27) 568*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) 569*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) 570*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) 571*fbb6c848SEzequiel Garcia #define VDPU_REG_VP8_QUANTER2 0x260 572*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) 573*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_4(x) (((x) & 0x7ff) << 11) 574*fbb6c848SEzequiel Garcia #define VDPU_REG_REF_PIC_QUANT_5(x) (((x) & 0x7ff) << 0) 575*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT1 0x264 576*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3(x) (((x) & 0x3ff) << 22) 577*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0(x) (((x) & 0x3ff) << 12) 578*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1(x) (((x) & 0x3ff) << 2) 579*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT2 0x268 580*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2(x) (((x) & 0x3ff) << 22) 581*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3(x) (((x) & 0x3ff) << 12) 582*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0(x) (((x) & 0x3ff) << 2) 583*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT3 0x26c 584*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1(x) (((x) & 0x3ff) << 22) 585*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2(x) (((x) & 0x3ff) << 12) 586*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3(x) (((x) & 0x3ff) << 2) 587*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT4 0x270 588*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0(x) (((x) & 0x3ff) << 22) 589*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1(x) (((x) & 0x3ff) << 12) 590*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2(x) (((x) & 0x3ff) << 2) 591*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT5 0x274 592*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3(x) (((x) & 0x3ff) << 22) 593*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0(x) (((x) & 0x3ff) << 12) 594*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1(x) (((x) & 0x3ff) << 2) 595*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT6 0x278 596*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2(x) (((x) & 0x3ff) << 22) 597*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3(x) (((x) & 0x3ff) << 12) 598*fbb6c848SEzequiel Garcia #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0(x) (((x) & 0x3ff) << 2) 599*fbb6c848SEzequiel Garcia 600*fbb6c848SEzequiel Garcia #endif /* ROCKCHIP_VPU2_REGS_H_ */ 601