1*73e00953SMoudy Ho /* SPDX-License-Identifier: GPL-2.0-only */ 2*73e00953SMoudy Ho /* 3*73e00953SMoudy Ho * Copyright (c) 2022 MediaTek Inc. 4*73e00953SMoudy Ho * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5*73e00953SMoudy Ho */ 6*73e00953SMoudy Ho 7*73e00953SMoudy Ho #ifndef __MDP_REG_TDSHP_H__ 8*73e00953SMoudy Ho #define __MDP_REG_TDSHP_H__ 9*73e00953SMoudy Ho 10*73e00953SMoudy Ho #define MDP_HIST_CFG_00 (0x064) 11*73e00953SMoudy Ho #define MDP_HIST_CFG_01 (0x068) 12*73e00953SMoudy Ho #define MDP_TDSHP_CTRL (0x100) 13*73e00953SMoudy Ho #define MDP_TDSHP_CFG (0x110) 14*73e00953SMoudy Ho #define MDP_TDSHP_INPUT_SIZE (0x120) 15*73e00953SMoudy Ho #define MDP_TDSHP_OUTPUT_OFFSET (0x124) 16*73e00953SMoudy Ho #define MDP_TDSHP_OUTPUT_SIZE (0x128) 17*73e00953SMoudy Ho #define MDP_LUMA_HIST_INIT (0x200) 18*73e00953SMoudy Ho #define MDP_DC_TWO_D_W1_RESULT_INIT (0x260) 19*73e00953SMoudy Ho #define MDP_CONTOUR_HIST_INIT (0x398) 20*73e00953SMoudy Ho 21*73e00953SMoudy Ho /* MASK */ 22*73e00953SMoudy Ho #define MDP_HIST_CFG_00_MASK (0xFFFFFFFF) 23*73e00953SMoudy Ho #define MDP_HIST_CFG_01_MASK (0xFFFFFFFF) 24*73e00953SMoudy Ho #define MDP_LUMA_HIST_MASK (0xFFFFFFFF) 25*73e00953SMoudy Ho #define MDP_TDSHP_CTRL_MASK (0x07) 26*73e00953SMoudy Ho #define MDP_TDSHP_CFG_MASK (0x03F7) 27*73e00953SMoudy Ho #define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF) 28*73e00953SMoudy Ho #define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF) 29*73e00953SMoudy Ho #define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF) 30*73e00953SMoudy Ho #define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF) 31*73e00953SMoudy Ho #define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF) 32*73e00953SMoudy Ho #define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF) 33*73e00953SMoudy Ho 34*73e00953SMoudy Ho #endif // __MDP_REG_TDSHP_H__ 35