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/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/linux/drivers/usb/gadget/udc/
H A Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
/linux/Documentation/devicetree/bindings/media/cec/
H A Damlogic,meson-gx-ao-cec.yaml87 reg = <0x00100 0x14>;
/linux/drivers/gpu/drm/arm/
H A Dmalidp_regs.h20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-85xx.h12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
20 #define _PAGE_READ 0x00001 /* H: Read permission (SR) */
21 #define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */
22 #define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */
23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24 #define _PAGE_EXEC 0x00010 /* H: SX permission */
25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
28 #define _PAGE_GUARDED 0x00080 /* H: G bit */
29 #define _PAGE_COHERENT 0x00100 /* H: M bit */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h12 #define DPCD_RC00_DPCD_REV 0x00000
13 #define DPCD_RC01_MAX_LINK_RATE 0x00001
14 #define DPCD_RC02 0x00002
15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
16 #define DPCD_RC02_TPS3_SUPPORTED 0x40
17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f
18 #define DPCD_RC03 0x00003
19 #define DPCD_RC03_TPS4_SUPPORTED 0x80
20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01
21 #define DPCD_RC0E 0x0000e
[all …]
/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/linux/tools/testing/selftests/kvm/include/x86_64/
H A Dapic.h16 #define APIC_DEFAULT_GPA 0xfee00000ULL
19 #define MSR_IA32_APICBASE 0x0000001b
23 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
26 #define APIC_BASE_MSR 0x800
28 #define APIC_ID 0x20
29 #define APIC_LVR 0x30
30 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
31 #define APIC_TASKPRI 0x80
32 #define APIC_PROCPRI 0xA0
33 #define APIC_EOI 0xB0
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi_phy_20nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
H A Ddsi_phy_28nm_8960.xml9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
20 <reg32 offset="0x00108" name="LNCK_CFG_2"/>
[all …]
H A Ddsi_phy_28nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
H A Ddsi_phy_7nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL_0"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
/linux/arch/x86/include/asm/
H A Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
[all …]
/linux/arch/mips/include/asm/
H A Dmsc01_ic.h18 #define MSC01_IC_RST_OFS 0x00008 /* Software reset */
19 #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
21 #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
23 #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
25 #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
27 #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
[all …]
/linux/drivers/memstick/host/
H A Dtifm_ms.c29 #define TIFM_MS_STAT_DRQ 0x04000
30 #define TIFM_MS_STAT_MSINT 0x02000
31 #define TIFM_MS_STAT_RDY 0x01000
32 #define TIFM_MS_STAT_CRC 0x00200
33 #define TIFM_MS_STAT_TOE 0x00100
34 #define TIFM_MS_STAT_EMP 0x00020
35 #define TIFM_MS_STAT_FUL 0x00010
36 #define TIFM_MS_STAT_CED 0x00008
37 #define TIFM_MS_STAT_ERR 0x00004
38 #define TIFM_MS_STAT_BRQ 0x00002
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.h60 #define FALSE 0
63 #define ALL_CHANNELS '\0'
64 #define ALL_TARGETS_MASK 0xFFFF
65 #define INITIATOR_WILDCARD (~0)
66 #define SCB_LIST_NULL 0xFF00
68 #define QOUTFIFO_ENTRY_VALID 0x80
69 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
76 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_regs.h13 #define DU0_REG_OFFSET 0x00000
14 #define DU1_REG_OFFSET 0x30000
15 #define DU2_REG_OFFSET 0x40000
16 #define DU3_REG_OFFSET 0x70000
22 #define DSYSR 0x00000 /* display 1 */
28 #define DSYSR_TVM_MASTER (0 << 6)
32 #define DSYSR_SCM_INT_NONE (0 << 4)
37 #define DSMR 0x00004
40 #define DSMR_DIPM_DISP (0 << 25)
50 #define DSMR_CDEM_CDE (0 << 13)
[all …]
/linux/drivers/scsi/ibmvscsi_tgt/
H A Dibmvscsi_tgt.h27 #define MSG_HI 0
36 #define SRP_VIOLATION 0x102 /* general error code */
55 #define LOCAL 0
70 #define ADAPT_SUCCESS 0L
139 SCSI_CDB = 0x01,
140 TASK_MANAGEMENT = 0x02,
141 /* MAD or addressed to port 0 */
142 ADAPTER_MAD = 0x04,
143 UNSET_TYPE = 0x08,
166 #define CMD_FAST_FAIL BIT(0)
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]

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