Lines Matching +full:0 +full:x00100
12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
26 # define INT_EP2DATASET 0x00080
27 # define INT_EP3DATASET 0x00100
28 #define INT_EPnNAK(n) (0x00100 << (n)) /* 0 < n < 4 */
29 # define INT_EP1NAK 0x00200
30 # define INT_EP2NAK 0x00400
31 # define INT_EP3NAK 0x00800
32 #define INT_SOF 0x01000
33 #define INT_ERR 0x02000
34 #define INT_MSTWRSET 0x04000
35 #define INT_MSTWREND 0x08000
36 #define INT_MSTWRTMOUT 0x10000
37 #define INT_MSTRDEND 0x20000
38 #define INT_SYSERROR 0x40000
39 #define INT_PWRDETECT 0x80000
47 #define MST_EOPB_DIS 0x0800
48 #define MST_EOPB_ENA 0x0400
49 #define MST_TIMEOUT_DIS 0x0200
50 #define MST_TIMEOUT_ENA 0x0100
51 #define MST_RD_EOPB 0x0080 /* write-only */
52 #define MST_RD_RESET 0x0040
53 #define MST_WR_RESET 0x0020
54 #define MST_RD_ENA 0x0004 /* 1:start, 0:ignore */
55 #define MST_WR_ENA 0x0002 /* 1:start, 0:ignore */
56 #define MST_CONNECTION 0x0001 /* 0 for ep1out/ep2in */
65 /* these values assume (dma_master & MST_CONNECTION) == 0 */
80 #define PW_DETECT 0x04
81 #define PW_RESETB 0x02
82 #define PW_PULLUP 0x01
84 u8 _reserved0 [0x1d8];
87 u32 ep_fifo [4]; /* 0x200 */
88 u8 _reserved1 [0x10];
90 u8 _reserved2 [0x10];
93 #define EPxSTATUS_TOGGLE 0x40
94 #define EPxSTATUS_SUSPEND 0x20
95 #define EPxSTATUS_EP_MASK (0x07<<2)
96 # define EPxSTATUS_EP_READY (0<<2)
104 #define EPxSTATUS_FIFO_DISABLE 0x02
105 #define EPxSTATUS_STAGE_ERROR 0x01
107 u8 _reserved3 [0x10];
110 #define DATASIZE 0x7f
111 u8 _reserved3a [0x10];
113 u8 _reserved3b [0x10];
115 u8 _reserved3c [0x10];
117 u8 _reserved4[0x30];
120 u32 bRequestType; /* 0x300 */
130 u32 SetupRecv; /* 0x320 */
141 #define USBSTATE_CONFIGURED 0x04
142 #define USBSTATE_ADDRESSED 0x02
143 #define USBSTATE_DEFAULT 0x01
147 u32 Command; /* 0x340 */
167 u32 reqmode; // 0x360 standard request mode, low 8 bits
175 #define G_REQMODE_GET_STATUS (1<<0)
178 u8 _reserved9[0x18];
179 u32 PortStatus; /* 0x380 */
186 u32 SetDescStall; /* 0x3a0 */
187 u8 _reserved13[0x45c];
190 #define DESC_LEN 0x80
191 u32 descriptors[DESC_LEN]; /* 0x800 */
192 u8 _reserved14[0x600];
273 do { } while (0)
280 do { } while (0)