Lines Matching +full:0 +full:x00100
18 #define MSC01_IC_RST_OFS 0x00008 /* Software reset */
19 #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
21 #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
23 #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
25 #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
27 #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
28 #define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */
29 #define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */
30 #define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */
31 #define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */
32 #define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
33 #define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */
34 #define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */
35 #define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */
36 #define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */
37 #define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */
38 #define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */
39 #define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */
40 #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41 #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42 #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43 #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
49 #define MSC01_IC_RST_RST_SHF 0
50 #define MSC01_IC_RST_RST_MSK 0x00000001
52 #define MSC01_IC_LVL_LVL_SHF 0
53 #define MSC01_IC_LVL_LVL_MSK 0x000000ff
55 #define MSC01_IC_LVL_SPUR_MSK 0x00010000
57 #define MSC01_IC_RAMW_RIPL_SHF 0
58 #define MSC01_IC_RAMW_RIPL_MSK 0x0000003f
60 #define MSC01_IC_RAMW_DATA_MSK 0x00000fc0
62 #define MSC01_IC_RAMW_ADDR_MSK 0x7e000000
64 #define MSC01_IC_RAMW_READ_MSK 0x80000000
66 #define MSC01_IC_OSB_OSB_SHF 0
67 #define MSC01_IC_OSB_OSB_MSK 0x000000ff
68 #define MSC01_IC_OSA_OSA_SHF 0
69 #define MSC01_IC_OSA_OSA_MSK 0x000000ff
70 #define MSC01_IC_GENA_GENA_SHF 0
71 #define MSC01_IC_GENA_GENA_MSK 0x00000001
73 #define MSC01_IC_CFG_DIS_SHF 0
74 #define MSC01_IC_CFG_DIS_MSK 0x00000001
77 #define MSC01_IC_CFG_SHFT_MSK 0x00000f00
78 #define MSC01_IC_TCFG_ENA_SHF 0
79 #define MSC01_IC_TCFG_ENA_MSK 0x00000001
82 #define MSC01_IC_TCFG_INT_MSK 0x00000100
85 #define MSC01_IC_TCFG_EDGE_MSK 0x00010000
87 #define MSC01_IC_SUP_PRI_SHF 0
88 #define MSC01_IC_SUP_PRI_MSK 0x00000007
90 #define MSC01_IC_SUP_EDGE_MSK 0x00000100
141 #define MSC01_IRQ_LEVEL 0