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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
H A Dtegra124-peripherals-opp.dtsi10 opp-supported-hw = <0x0003>;
16 opp-supported-hw = <0x0008>;
22 opp-supported-hw = <0x0010>;
28 opp-supported-hw = <0x0004>;
34 opp-supported-hw = <0x0003>;
40 opp-supported-hw = <0x0008>;
46 opp-supported-hw = <0x0010>;
52 opp-supported-hw = <0x0004>;
58 opp-supported-hw = <0x0003>;
64 opp-supported-hw = <0x0008>;
[all …]
/linux/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/linux/sound/soc/qcom/
H A Dlpass-ipq806x.c95 return 0; in ipq806x_lpass_exit()
108 return 0; in ipq806x_lpass_free_dma_channel()
112 .i2sctrl_reg_base = 0x0010,
113 .i2sctrl_reg_stride = 0x04,
115 .irq_reg_base = 0x3000,
116 .irq_reg_stride = 0x1000,
118 .rdma_reg_base = 0x6000,
119 .rdma_reg_stride = 0x1000,
121 .wrdma_reg_base = 0xB000,
122 .wrdma_reg_stride = 0x1000,
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]
H A Dpinctrl-mt8186.c13 * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
14 * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
15 * iocfg[6]:0x10002C00.
20 PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
26 PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
30 PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
34 PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
38 PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
42 PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
43 PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-infracfg.c19 #define MT7988_INFRA_RST0_SET_OFFSET 0x70
20 #define MT7988_INFRA_RST1_SET_OFFSET 0x80
60 infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
62 infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
64 infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
66 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
68 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
70 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
71 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72 0x0010, 0x0014, 14, 2, -1, -1, -1),
[all …]
H A Dclk-mt7981-infracfg.c48 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
51 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
54 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
57 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
60 infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
63 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
66 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
69 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
72 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
75 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
[all …]
H A Dclk-mt7986-infracfg.c41 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50 infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53 infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
66 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
71 .set_ofs = 0x40,
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132-peripherals-opp.dtsi11 opp-supported-hw = <0x0003>;
17 opp-supported-hw = <0x0008>;
23 opp-supported-hw = <0x0010>;
29 opp-supported-hw = <0x0004>;
35 opp-supported-hw = <0x0003>;
41 opp-supported-hw = <0x0008>;
47 opp-supported-hw = <0x0010>;
53 opp-supported-hw = <0x0004>;
59 opp-supported-hw = <0x0003>;
65 opp-supported-hw = <0x0008>;
[all …]
/linux/sound/soc/codecs/
H A Dwm8990.h16 #define WM8990_RESET 0x00
17 #define WM8990_POWER_MANAGEMENT_1 0x01
18 #define WM8990_POWER_MANAGEMENT_2 0x02
19 #define WM8990_POWER_MANAGEMENT_3 0x03
20 #define WM8990_AUDIO_INTERFACE_1 0x04
21 #define WM8990_AUDIO_INTERFACE_2 0x05
22 #define WM8990_CLOCKING_1 0x06
23 #define WM8990_CLOCKING_2 0x07
24 #define WM8990_AUDIO_INTERFACE_3 0x08
25 #define WM8990_AUDIO_INTERFACE_4 0x09
[all …]
H A Dwm8991.h16 #define WM8991_RESET 0x00
17 #define WM8991_POWER_MANAGEMENT_1 0x01
18 #define WM8991_POWER_MANAGEMENT_2 0x02
19 #define WM8991_POWER_MANAGEMENT_3 0x03
20 #define WM8991_AUDIO_INTERFACE_1 0x04
21 #define WM8991_AUDIO_INTERFACE_2 0x05
22 #define WM8991_CLOCKING_1 0x06
23 #define WM8991_CLOCKING_2 0x07
24 #define WM8991_AUDIO_INTERFACE_3 0x08
25 #define WM8991_AUDIO_INTERFACE_4 0x09
[all …]
H A Dwm8737.h16 #define WM8737_LEFT_PGA_VOLUME 0x00
17 #define WM8737_RIGHT_PGA_VOLUME 0x01
18 #define WM8737_AUDIO_PATH_L 0x02
19 #define WM8737_AUDIO_PATH_R 0x03
20 #define WM8737_3D_ENHANCE 0x04
21 #define WM8737_ADC_CONTROL 0x05
22 #define WM8737_POWER_MANAGEMENT 0x06
23 #define WM8737_AUDIO_FORMAT 0x07
24 #define WM8737_CLOCKING 0x08
25 #define WM8737_MIC_PREAMP_CONTROL 0x09
[all …]
/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
H A Dwm8904.h14 #define WM8904_GPIO_NO_CONFIG 0x8000
17 * R6 (0x06) - Mic Bias Control 0
19 #define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
22 #define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
25 #define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */
26 #define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
29 #define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
30 #define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
31 #define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
35 * R7 (0x07) - Mic Bias Control 1
[all …]
/linux/sound/pci/oxygen/
H A Dcm9780.h5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
/linux/include/linux/mfd/
H A Dwm8400-audio.h14 * R2 (0x02) - Power Management (1)
16 #define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
17 #define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
20 #define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
21 #define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
24 #define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
25 #define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
28 #define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
29 #define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
32 #define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
[all …]
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/include/linux/mfd/wm831x/
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux/drivers/net/can/softing/
H A Dsofting_cs.c30 .manf = 0x0168, .prod = 0x001,
34 .dpram_size = 0x0800,
35 .boot = {0x0000, 0x000000, fw_dir "bcard.bin",},
36 .load = {0x0120, 0x00f600, fw_dir "ldcard.bin",},
37 .app = {0x0010, 0x0d0000, fw_dir "cancard.bin",},
42 .manf = 0x0168, .prod = 0x002,
46 .dpram_size = 0x0800,
47 .boot = {0x0000, 0x000000, fw_dir "bcard.bin",},
48 .load = {0x0120, 0x00f600, fw_dir "ldcard.bin",},
49 .app = {0x0010, 0x0d0000, fw_dir "cancard.bin",},
[all …]
/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm_mpu44xx.h27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
[all …]

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