Lines Matching +full:0 +full:x0010
48 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
51 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
54 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
57 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
60 infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
63 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
66 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
69 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
72 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
75 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
79 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
84 .set_ofs = 0x40,
85 .clr_ofs = 0x44,
86 .sta_ofs = 0x48,
90 .set_ofs = 0x50,
91 .clr_ofs = 0x54,
92 .sta_ofs = 0x58,
96 .set_ofs = 0x60,
97 .clr_ofs = 0x64,
98 .sta_ofs = 0x68,
124 GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
144 GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
171 GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),