Lines Matching +full:0 +full:x0010
15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
51 * R116 (0x74) - GPIO Control 1
53 #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
56 #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
57 #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
60 #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
61 #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
64 #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
65 #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
68 #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
69 #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
72 #define WM8903_GP1_PD 0x0008 /* GP1_PD */
73 #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
76 #define WM8903_GP1_PU 0x0004 /* GP1_PU */
77 #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
80 #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
81 #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
84 #define WM8903_GP1_DB 0x0001 /* GP1_DB */
85 #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
86 #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
90 * R117 (0x75) - GPIO Control 2
92 #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
95 #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
96 #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
99 #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
100 #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
103 #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
104 #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
107 #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
108 #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
111 #define WM8903_GP2_PD 0x0008 /* GP2_PD */
112 #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
115 #define WM8903_GP2_PU 0x0004 /* GP2_PU */
116 #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
119 #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
120 #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
123 #define WM8903_GP2_DB 0x0001 /* GP2_DB */
124 #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
125 #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
129 * R118 (0x76) - GPIO Control 3
131 #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
134 #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
135 #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
138 #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
139 #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
142 #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
143 #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
146 #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
147 #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
150 #define WM8903_GP3_PD 0x0008 /* GP3_PD */
151 #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
154 #define WM8903_GP3_PU 0x0004 /* GP3_PU */
155 #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
158 #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
159 #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
162 #define WM8903_GP3_DB 0x0001 /* GP3_DB */
163 #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
164 #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
168 * R119 (0x77) - GPIO Control 4
170 #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
173 #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
174 #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
177 #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
178 #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
181 #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
182 #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
185 #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
186 #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
189 #define WM8903_GP4_PD 0x0008 /* GP4_PD */
190 #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
193 #define WM8903_GP4_PU 0x0004 /* GP4_PU */
194 #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
197 #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
198 #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
201 #define WM8903_GP4_DB 0x0001 /* GP4_DB */
202 #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
203 #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
207 * R120 (0x78) - GPIO Control 5
209 #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
212 #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
213 #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
216 #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
217 #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
220 #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
221 #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
224 #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
225 #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
228 #define WM8903_GP5_PD 0x0008 /* GP5_PD */
229 #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
232 #define WM8903_GP5_PU 0x0004 /* GP5_PU */
233 #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
236 #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
237 #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
240 #define WM8903_GP5_DB 0x0001 /* GP5_DB */
241 #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
242 #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */