Home
last modified time | relevance | path

Searched +full:0 +full:x000ff000 (Results 1 – 25 of 38) sorted by relevance

12

/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_acc.c17 u32 hi = 0, lo = value; in pci_acc_write_reg()
23 lo |= (0x03 << 8); in pci_acc_write_reg()
25 lo &= ~(0x03 << 8); in pci_acc_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_acc_write_reg()
42 } else if (value & 0x01) { in pci_acc_write_reg()
43 value &= 0xfffffffc; in pci_acc_write_reg()
44 hi = 0xA0000000 | ((value & 0x000ff000) >> 12); in pci_acc_write_reg()
45 lo = 0x000fff80 | ((value & 0x00000fff) << 20); in pci_acc_write_reg()
52 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); in pci_acc_write_reg()
65 u32 conf_data = 0; in pci_acc_read_reg()
[all …]
H A Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
[all …]
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/linux/drivers/parisc/
H A Diosapic.c161 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
164 #define IOSAPIC_REG_SELECT 0x00
165 #define IOSAPIC_REG_WINDOW 0x10
166 #define IOSAPIC_REG_EOI 0x40
168 #define IOSAPIC_REG_VERSION 0x1
170 #define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
171 #define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
185 #define IOSAPIC_VERSION_MASK 0x000000ff
188 #define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
189 #define IOSAPIC_MAX_ENTRY_SHIFT 0x10
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dhw_common.c24 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in rtl92d_stop_tx_beacon()
25 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in rtl92d_stop_tx_beacon()
27 tmp1byte &= ~(BIT(0)); in rtl92d_stop_tx_beacon()
39 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in rtl92d_resume_tx_beacon()
40 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in rtl92d_resume_tx_beacon()
42 tmp1byte |= BIT(0); in rtl92d_resume_tx_beacon()
66 val_rcr &= 0x00070000; in rtl92d_get_hw_reg()
113 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92d_set_hw_reg()
119 u16 rate_cfg = ((u16 *)val)[0]; in rtl92d_set_hw_reg()
120 u8 rate_index = 0; in rtl92d_set_hw_reg()
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/drivers/nvmem/
H A Dimx-ocotp.c27 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
30 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
34 #define IMX_OCOTP_ADDR_CTRL 0x0000
35 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
36 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
37 #define IMX_OCOTP_ADDR_TIMING 0x0010
38 #define IMX_OCOTP_ADDR_DATA0 0x0020
39 #define IMX_OCOTP_ADDR_DATA1 0x0030
40 #define IMX_OCOTP_ADDR_DATA2 0x0040
41 #define IMX_OCOTP_ADDR_DATA3 0x0050
[all …]
/linux/drivers/video/fbdev/
H A Dpxa168fb.h6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dhw.c42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ee_stop_tx_beacon()
44 tmp &= ~(BIT(0)); in _rtl92ee_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ee_resume_tx_beacon()
57 tmp |= BIT(0); in _rtl92ee_resume_tx_beacon()
63 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ee_enable_bcn_sub_func()
68 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ee_disable_bcn_sub_func()
77 u32 count = 0, isr_regaddr, content; in _rtl92ee_set_fw_clock_on()
120 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); in _rtl92ee_set_fw_clock_on()
163 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { in _rtl92ee_set_fw_clock_off()
183 rtl_write_word(rtlpriv, REG_HISR, 0x0100); in _rtl92ee_set_fw_clock_off()
[all …]
/linux/drivers/iommu/
H A Dfsl_pamu.c21 #define OMI_QMAN 0x00
22 #define OMI_FMAN 0x01
23 #define OMI_QMAN_PRIV 0x02
24 #define OMI_CAAM 0x03
90 * Returns 0 upon success else error code < 0 returned
113 return 0; in pamu_enable_liodn()
120 * Returns 0 upon success else error code < 0 returned
135 return 0; in pamu_disable_liodn()
177 return 0; in pamu_update_paace_stash()
184 * @omi: Operation mapping index -- if ~omi == 0 then omi not defined
[all …]
/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_crtc.c28 #define TILCDC_PALETTE_FIRST_ENTRY 0x4000
71 gem = drm_fb_dma_get_gem_obj(fb, 0); in set_scanout()
73 start = gem->dma_addr + fb->offsets[0] + in set_scanout()
74 crtc->y * fb->pitches[0] + in set_scanout()
75 crtc->x * fb->format->cpp[0]; in set_scanout()
77 end = start + (crtc->mode.vdisplay * fb->pitches[0]); in set_scanout()
94 * should still be loaded. The first 16-bit entry must be 0x4000 while
125 tilcdc_clear_irqstatus(dev, 0xffffffff); in tilcdc_crtc_load_palette()
130 if (ret == 0) in tilcdc_crtc_load_palette()
145 tilcdc_clear_irqstatus(dev, 0xffffffff); in tilcdc_crtc_enable_irqs()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhw.c46 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl8723e_stop_tx_beacon()
48 tmp1byte &= ~(BIT(0)); in _rtl8723e_stop_tx_beacon()
59 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl8723e_resume_tx_beacon()
67 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl8723e_enable_bcn_sub_func()
72 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl8723e_disable_bcn_sub_func()
99 val_rcr &= 0x00070000; in rtl8723e_get_hw_reg()
142 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl8723e_set_hw_reg()
149 u16 b_rate_cfg = ((u16 *)val)[0]; in rtl8723e_set_hw_reg()
150 u8 rate_index = 0; in rtl8723e_set_hw_reg()
152 b_rate_cfg = b_rate_cfg & 0x15f; in rtl8723e_set_hw_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dhw.c42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ce_stop_tx_beacon()
44 tmp1byte &= ~(BIT(0)); in _rtl92ce_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_resume_tx_beacon()
57 tmp1byte |= BIT(0); in _rtl92ce_resume_tx_beacon()
63 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ce_enable_bcn_sub_func()
68 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ce_disable_bcn_sub_func()
95 val_rcr &= 0x00070000; in rtl92ce_get_hw_reg()
138 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92ce_set_hw_reg()
145 u16 rate_cfg = ((u16 *) val)[0]; in rtl92ce_set_hw_reg()
146 u8 rate_index = 0; in rtl92ce_set_hw_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dhw.c107 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92cu_read_txpower_info_from_hwpg()
108 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
127 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
133 (tempval & 0xf); in _rtl92cu_read_txpower_info_from_hwpg()
135 ((tempval & 0xf0) >> 4); in _rtl92cu_read_txpower_info_from_hwpg()
137 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
138 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
144 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
145 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dhw.c42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl88ee_stop_tx_beacon()
44 tmp1byte &= ~(BIT(0)); in _rtl88ee_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl88ee_resume_tx_beacon()
57 tmp1byte |= BIT(0); in _rtl88ee_resume_tx_beacon()
63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl88ee_enable_bcn_sub_func()
94 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl88ee_disable_bcn_sub_func()
103 u32 count = 0, isr_regaddr, content; in _rtl88ee_set_fw_clock_on()
144 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); in _rtl88ee_set_fw_clock_on()
188 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { in _rtl88ee_set_fw_clock_off()
209 rtl_write_word(rtlpriv, REG_HISR, 0x0100); in _rtl88ee_set_fw_clock_off()
[all …]

12