28 #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
31 #define IMX_OCOTP_OFFSET_PER_WORD	0x10  /* Offset between the start addr
35 #define IMX_OCOTP_ADDR_CTRL		0x0000
36 #define IMX_OCOTP_ADDR_CTRL_SET		0x0004
37 #define IMX_OCOTP_ADDR_CTRL_CLR		0x0008
38 #define IMX_OCOTP_ADDR_TIMING		0x0010
39 #define IMX_OCOTP_ADDR_DATA0		0x0020
40 #define IMX_OCOTP_ADDR_DATA1		0x0030
41 #define IMX_OCOTP_ADDR_DATA2		0x0040
42 #define IMX_OCOTP_ADDR_DATA3		0x0050
44 #define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
45 #define IMX_OCOTP_BM_CTRL_BUSY		0x00000100
46 #define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
47 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400
49 #define IMX_OCOTP_BM_CTRL_ADDR_8MP		0x000001FF
50 #define IMX_OCOTP_BM_CTRL_BUSY_8MP		0x00000200
51 #define IMX_OCOTP_BM_CTRL_ERROR_8MP		0x00000400
52 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP	0x00000800
75 #define IMX_OCOTP_WR_UNLOCK		0x3E770000
76 #define IMX_OCOTP_READ_LOCKED_VAL	0xBADABADA
114 	for (count = 10000; count >= 0; count--) {  in imx_ocotp_wait_for_busy()
121 	if (count < 0) {  in imx_ocotp_wait_for_busy()
141 	return 0;  in imx_ocotp_wait_for_busy()
183 	if (ret < 0) {  in imx_ocotp_read()
190 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_read()
191 	if (ret < 0) {  in imx_ocotp_read()
201 		 * For "read locked" registers 0xBADABADA will be returned and  in imx_ocotp_read()
233 		for (i = 0; i < bytes / 2; i++)  in imx_ocotp_cell_pp()
237 	return 0;  in imx_ocotp_cell_pp()
284 	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;  in imx_ocotp_set_imx6_timing()
285 	timing |= strobe_prog & 0x00000FFF;  in imx_ocotp_set_imx6_timing()
286 	timing |= (relax       << 12) & 0x0000F000;  in imx_ocotp_set_imx6_timing()
287 	timing |= (strobe_read << 16) & 0x003F0000;  in imx_ocotp_set_imx6_timing()
307 	timing = strobe_prog & 0x00000FFF;  in imx_ocotp_set_imx7_timing()
308 	timing |= (fsource << 12) & 0x000FF000;  in imx_ocotp_set_imx7_timing()
322 	u8 word = 0;  in imx_ocotp_write()
332 	if (ret < 0) {  in imx_ocotp_write()
347 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_write()
348 	if (ret < 0) {  in imx_ocotp_write()
360 	if (priv->params->bank_address_words != 0) {  in imx_ocotp_write()
393 	 * fields with 0's will be ignored. At the same time that the write is  in imx_ocotp_write()
407 	if (priv->params->bank_address_words != 0) {  in imx_ocotp_write()
410 		case 0:  in imx_ocotp_write()
411 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
412 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
413 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
418 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
419 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
420 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
423 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
425 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
426 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
429 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
430 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
432 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
447 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_write()
448 	if (ret < 0) {  in imx_ocotp_write()
471 	if (ret < 0)  in imx_ocotp_write()
477 	return ret < 0 ? ret : bytes;  in imx_ocotp_write()
491 	.bank_address_words = 0,
498 	.bank_address_words = 0,
505 	.bank_address_words = 0,
512 	.bank_address_words = 0,
519 	.bank_address_words = 0,
526 	.bank_address_words = 0,
540 	.bank_address_words = 0,
546 	.bank_address_words = 0,
553 	.bank_address_words = 0,
560 	.bank_address_words = 0,
567 	.bank_address_words = 0,
607 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in imx_ocotp_probe()