Lines Matching +full:0 +full:x000ff000
107 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92cu_read_txpower_info_from_hwpg()
108 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
127 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
133 (tempval & 0xf); in _rtl92cu_read_txpower_info_from_hwpg()
135 ((tempval & 0xf0) >> 4); in _rtl92cu_read_txpower_info_from_hwpg()
137 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
138 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
144 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
145 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
147 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
151 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
152 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
154 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
158 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92cu_read_txpower_info_from_hwpg()
159 for (i = 0; i < 14; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
168 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][index], 0); in _rtl92cu_read_txpower_info_from_hwpg()
170 for (i = 0; i < 14; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
172 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, in _rtl92cu_read_txpower_info_from_hwpg()
178 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
185 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; in _rtl92cu_read_txpower_info_from_hwpg()
186 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; in _rtl92cu_read_txpower_info_from_hwpg()
189 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92cu_read_txpower_info_from_hwpg()
190 for (i = 0; i < 14; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
195 & 0xf); in _rtl92cu_read_txpower_info_from_hwpg()
198 & 0xf); in _rtl92cu_read_txpower_info_from_hwpg()
202 & 0xf0) >> 4); in _rtl92cu_read_txpower_info_from_hwpg()
205 & 0xf0) >> 4); in _rtl92cu_read_txpower_info_from_hwpg()
208 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
212 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
217 for (i = 0; i < 14; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
223 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92cu_read_txpower_info_from_hwpg()
225 ((tempval >> 4) & 0xF); in _rtl92cu_read_txpower_info_from_hwpg()
227 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; in _rtl92cu_read_txpower_info_from_hwpg()
229 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; in _rtl92cu_read_txpower_info_from_hwpg()
235 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92cu_read_txpower_info_from_hwpg()
237 ((tempval >> 4) & 0xF); in _rtl92cu_read_txpower_info_from_hwpg()
241 for (i = 0; i < 14; i++) in _rtl92cu_read_txpower_info_from_hwpg()
243 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
245 for (i = 0; i < 14; i++) in _rtl92cu_read_txpower_info_from_hwpg()
247 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
249 for (i = 0; i < 14; i++) in _rtl92cu_read_txpower_info_from_hwpg()
251 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
253 for (i = 0; i < 14; i++) in _rtl92cu_read_txpower_info_from_hwpg()
255 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
258 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); in _rtl92cu_read_txpower_info_from_hwpg()
260 rtlefuse->eeprom_regulatory = 0; in _rtl92cu_read_txpower_info_from_hwpg()
262 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); in _rtl92cu_read_txpower_info_from_hwpg()
271 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
278 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); in _rtl92cu_read_txpower_info_from_hwpg()
279 if (rtlefuse->eeprom_thermalmeter < 0x06 || in _rtl92cu_read_txpower_info_from_hwpg()
280 rtlefuse->eeprom_thermalmeter > 0x1c) in _rtl92cu_read_txpower_info_from_hwpg()
281 rtlefuse->eeprom_thermalmeter = 0x12; in _rtl92cu_read_txpower_info_from_hwpg()
282 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) in _rtl92cu_read_txpower_info_from_hwpg()
284 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; in _rtl92cu_read_txpower_info_from_hwpg()
286 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); in _rtl92cu_read_txpower_info_from_hwpg()
316 0}; in _rtl92cu_read_adapter_info()
334 if (rtlefuse->eeprom_did == 0x8176) { in _rtl92cu_read_adapter_info()
335 if ((rtlefuse->eeprom_svid == 0x103C && in _rtl92cu_read_adapter_info()
336 rtlefuse->eeprom_smid == 0x1629)) in _rtl92cu_read_adapter_info()
378 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", in _rtl92cu_hal_customized_behavior()
408 int status = 0; in _rtl92cu_init_power_on()
412 u32 pollingcount = 0; in _rtl92cu_init_power_on()
425 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ in _rtl92cu_init_power_on()
426 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); in _rtl92cu_init_power_on()
429 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92cu_init_power_on()
432 if (0 == (value8 & LDV12_EN)) { in _rtl92cu_init_power_on()
436 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", in _rtl92cu_init_power_on()
444 pollingcount = 0; in _rtl92cu_init_power_on()
459 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); in _rtl92cu_init_power_on()
465 pollingcount = 0; in _rtl92cu_init_power_on()
488 u32 numhq = 0; in _rtl92cu_init_queue_reserved_page()
489 u32 numlq = 0; in _rtl92cu_init_queue_reserved_page()
490 u32 numnq = 0; in _rtl92cu_init_queue_reserved_page()
534 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); in _rtl92c_init_trx_buffer()
544 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); in _rtl92c_init_chipn_reg_priority()
573 pr_info("Tx queue select: 0x%02x\n", queue_sel); in _rtl92cu_init_chipn_one_out_ep_priority()
609 pr_info("Tx queue select: 0x%02x\n", queue_sel); in _rtl92cu_init_chipn_two_out_ep_priority()
625 pr_info("Tx queue select :0x%02x..\n", queue_sel); in _rtl92cu_init_chipn_three_out_ep_priority()
652 u8 hq_sele = 0; in _rtl92cu_init_chipt_queue_priority()
662 hq_sele = 0; in _rtl92cu_init_chipt_queue_priority()
674 pr_info("Tx queue select :0x%02x..\n", hq_sele); in _rtl92cu_init_chipt_queue_priority()
700 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); in _rtl92cu_init_wmac_setting()
701 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); in _rtl92cu_init_wmac_setting()
703 value16 = 0xFFFF; in _rtl92cu_init_wmac_setting()
706 /* Reject all control frame - default value is 0 */ in _rtl92cu_init_wmac_setting()
707 value16 = 0x0; in _rtl92cu_init_wmac_setting()
711 value16 = 0xFFFF; in _rtl92cu_init_wmac_setting()
721 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); in _rtl92cu_init_beacon_parameters()
724 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); in _rtl92cu_init_beacon_parameters()
731 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); in _rtl92cu_init_beacon_parameters()
733 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); in _rtl92cu_init_beacon_parameters()
742 int err = 0; in _rtl92cu_init_mac()
780 u8 sec_reg_value = 0x0; in rtl92cu_enable_hw_security_config()
799 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92cu_enable_hw_security_config()
811 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); in _rtl92cu_hw_configure()
812 rtl_write_byte(rtlpriv, 0x15, 0xe9); in _rtl92cu_hw_configure()
814 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ in _rtl92cu_hw_configure()
815 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92cu_hw_configure()
817 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); in _rtl92cu_hw_configure()
818 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); in _rtl92cu_hw_configure()
819 rtl_write_byte(rtlpriv, 0xfe42, 0x80); in _rtl92cu_hw_configure()
820 rtlusb->reg_bcn_ctrl_val = 0x18; in _rtl92cu_hw_configure()
831 pa_setting = efuse_read_1byte(hw, 0x1FA); in _initpabias()
832 if (!(pa_setting & BIT(0))) { in _initpabias()
833 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); in _initpabias()
834 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); in _initpabias()
835 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); in _initpabias()
836 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); in _initpabias()
840 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); in _initpabias()
841 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); in _initpabias()
842 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); in _initpabias()
843 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); in _initpabias()
846 pa_setting = rtl_read_byte(rtlpriv, 0x16); in _initpabias()
847 pa_setting &= 0x0F; in _initpabias()
848 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); in _initpabias()
859 int err = 0; in rtl92cu_hw_init()
888 rtlhal->last_hmeboxnum = 0; /* h2c */ in rtl92cu_hw_init()
896 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); in rtl92cu_hw_init()
897 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); in rtl92cu_hw_init()
899 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, in rtl92cu_hw_init()
932 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue in disable_rfafeandresetbb()
933 b. RF path 0 offset 0x00 = 0x00 disable RF in disable_rfafeandresetbb()
934 c. APSD_CTRL 0x600[7:0] = 0x40 in disable_rfafeandresetbb()
935 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine in disable_rfafeandresetbb()
936 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine in disable_rfafeandresetbb()
938 u8 erfpath = 0, value8 = 0; in disable_rfafeandresetbb()
940 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in disable_rfafeandresetbb()
941 rtl_set_rfreg(hw, (enum radio_path)erfpath, 0x0, MASKBYTE0, 0x0); in disable_rfafeandresetbb()
944 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ in disable_rfafeandresetbb()
945 value8 = 0; in disable_rfafeandresetbb()
947 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ in disable_rfafeandresetbb()
949 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ in disable_rfafeandresetbb()
957 if (rtlhal->fw_version <= 0x20) { in _resetdigitalprocedure1()
959 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status in _resetdigitalprocedure1()
960 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) in _resetdigitalprocedure1()
961 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE in _resetdigitalprocedure1()
962 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) in _resetdigitalprocedure1()
964 u16 valu16 = 0; in _resetdigitalprocedure1()
966 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); in _resetdigitalprocedure1()
970 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; in _resetdigitalprocedure1()
977 u8 retry_cnts = 0; in _resetdigitalprocedure1()
982 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); in _resetdigitalprocedure1()
984 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); in _resetdigitalprocedure1()
995 0x50); in _resetdigitalprocedure1()
1000 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); in _resetdigitalprocedure1()
1001 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); in _resetdigitalprocedure1()
1006 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock in _resetdigitalprocedure1()
1007 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL in _resetdigitalprocedure1()
1008 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK in _resetdigitalprocedure1()
1009 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON in _resetdigitalprocedure1()
1011 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); in _resetdigitalprocedure1()
1012 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _resetdigitalprocedure1()
1013 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); in _resetdigitalprocedure1()
1014 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); in _resetdigitalprocedure1()
1022 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction in _resetdigitalprocedure2()
1023 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock in _resetdigitalprocedure2()
1024 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON in _resetdigitalprocedure2()
1026 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); in _resetdigitalprocedure2()
1027 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); in _resetdigitalprocedure2()
1034 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 in _disablegpio()
1035 k. Value = GPIO_PIN_CTRL[7:0] in _disablegpio()
1036 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level in _disablegpio()
1037 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 in _disablegpio()
1038 n. LEDCFG 0x4C[15:0] = 0x8080 in _disablegpio()
1044 /* 1. Disable GPIO[7:0] */ in _disablegpio()
1045 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); in _disablegpio()
1046 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; in _disablegpio()
1047 value8 = (u8)(value32&0x000000FF); in _disablegpio()
1048 value32 |= ((value8<<8) | 0x00FF0000); in _disablegpio()
1051 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); in _disablegpio()
1052 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; in _disablegpio()
1053 value8 = (u8)(value16&0x000F); in _disablegpio()
1054 value16 |= ((value8<<4) | 0x0780); in _disablegpio()
1057 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _disablegpio()
1063 u16 value16 = 0; in disable_analog()
1064 u8 value8 = 0; in disable_analog()
1068 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power in disable_analog()
1069 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power in disable_analog()
1073 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); in disable_analog()
1080 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode in disable_analog()
1081 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend in disable_analog()
1083 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in disable_analog()
1086 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); in disable_analog()
1130 u8 tmp1byte = 0; in _rtl92cu_stop_tx_beacon()
1136 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92cu_stop_tx_beacon()
1138 tmp1byte &= ~(BIT(0)); in _rtl92cu_stop_tx_beacon()
1150 u8 tmp1byte = 0; in _rtl92cu_resume_tx_beacon()
1156 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92cu_resume_tx_beacon()
1158 tmp1byte |= BIT(0); in _rtl92cu_resume_tx_beacon()
1172 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92cu_enable_bcn_sub_func()
1174 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); in _rtl92cu_enable_bcn_sub_func()
1183 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92cu_disable_bcn_sub_func()
1185 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); in _rtl92cu_disable_bcn_sub_func()
1195 bt_msr &= 0xfc; in _rtl92cu_set_media_status()
1238 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92cu_set_media_status()
1240 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92cu_set_media_status()
1241 return 0; in _rtl92cu_set_media_status()
1291 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); in rtl92cu_set_check_bssid()
1305 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); in rtl92cu_set_check_bssid()
1325 return 0; in rtl92cu_set_network_type()
1332 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); in _beacon_function_enable()
1333 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); in _beacon_function_enable()
1349 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in rtl92cu_set_beacon_related_registers()
1370 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); in rtl92cu_set_beacon_related_registers()
1371 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); in rtl92cu_set_beacon_related_registers()
1415 val_rcr &= 0x00070000; in rtl92cu_get_hw_reg()
1476 u8 idx = 0; in rtl92cu_set_hw_reg()
1480 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92cu_set_hw_reg()
1487 u16 rate_cfg = ((u16 *) val)[0]; in rtl92cu_set_hw_reg()
1488 u8 rate_index = 0; in rtl92cu_set_hw_reg()
1490 rate_cfg &= 0x15f; in rtl92cu_set_hw_reg()
1493 * && ((rate_cfg & 0x150) == 0)) { in rtl92cu_set_hw_reg()
1494 * rate_cfg |= 0x010; in rtl92cu_set_hw_reg()
1496 rate_cfg |= 0x01; in rtl92cu_set_hw_reg()
1497 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); in rtl92cu_set_hw_reg()
1499 (rate_cfg >> 8) & 0xff); in rtl92cu_set_hw_reg()
1500 while (rate_cfg > 0x1) { in rtl92cu_set_hw_reg()
1509 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92cu_set_hw_reg()
1516 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); in rtl92cu_set_hw_reg()
1518 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92cu_set_hw_reg()
1519 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92cu_set_hw_reg()
1520 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); in rtl92cu_set_hw_reg()
1521 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); in rtl92cu_set_hw_reg()
1528 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92cu_set_hw_reg()
1530 "HW_VAR_SLOT_TIME %x\n", val[0]); in rtl92cu_set_hw_reg()
1532 for (e_aci = 0; e_aci < AC_MAX; e_aci++) in rtl92cu_set_hw_reg()
1542 reg_tmp = 0; in rtl92cu_set_hw_reg()
1544 reg_tmp |= 0x80; in rtl92cu_set_hw_reg()
1557 sec_min_space = 0; in rtl92cu_set_hw_reg()
1571 0xf8) | in rtl92cu_set_hw_reg()
1586 density_to_set &= 0x1f; in rtl92cu_set_hw_reg()
1587 mac->min_space_cfg &= 0x07; in rtl92cu_set_hw_reg()
1597 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; in rtl92cu_set_hw_reg()
1600 u8 index = 0; in rtl92cu_set_hw_reg()
1606 if (factor_toset > 0xf) in rtl92cu_set_hw_reg()
1607 factor_toset = 0xf; in rtl92cu_set_hw_reg()
1608 for (index = 0; index < 4; index++) { in rtl92cu_set_hw_reg()
1609 if ((p_regtoset[index] & 0xf0) > in rtl92cu_set_hw_reg()
1612 (p_regtoset[index] & 0x0f) in rtl92cu_set_hw_reg()
1614 if ((p_regtoset[index] & 0x0f) > in rtl92cu_set_hw_reg()
1617 (p_regtoset[index] & 0xf0) in rtl92cu_set_hw_reg()
1637 u4b_ac_param |= (u32) ((cw_min & 0xF) << in rtl92cu_set_hw_reg()
1639 u4b_ac_param |= (u32) ((cw_max & 0xF) << in rtl92cu_set_hw_reg()
1670 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92cu_set_hw_reg()
1671 mac->rx_conf = ((u32 *) (val))[0]; in rtl92cu_set_hw_reg()
1673 "### Set RCR(0x%08x) ###\n", mac->rx_conf); in rtl92cu_set_hw_reg()
1677 u8 retry_limit = val[0]; in rtl92cu_set_hw_reg()
1683 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", in rtl92cu_set_hw_reg()
1688 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92cu_set_hw_reg()
1732 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); in rtl92cu_set_hw_reg()
1733 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92cu_set_hw_reg()
1734 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92cu_set_hw_reg()
1743 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92cu_set_hw_reg()
1744 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92cu_set_hw_reg()
1749 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92cu_set_hw_reg()
1758 u2btmp &= 0xC000; in rtl92cu_set_hw_reg()
1764 u8 btype_ibss = val[0]; in rtl92cu_set_hw_reg()
1768 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92cu_set_hw_reg()
1770 0xffffffff)); in rtl92cu_set_hw_reg()
1772 (u32)((mac->tsf >> 32) & 0xffffffff)); in rtl92cu_set_hw_reg()
1773 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92cu_set_hw_reg()
1793 array[0] = 0xff; in rtl92cu_set_hw_reg()
1813 u8 ratr_index = 0; in rtl92cu_update_hal_rate_table()
1820 1 : 0; in rtl92cu_update_hal_rate_table()
1822 1 : 0; in rtl92cu_update_hal_rate_table()
1828 ratr_value = sta->deflink.supp_rates[0]; in rtl92cu_update_hal_rate_table()
1830 ratr_value = 0xfff; in rtl92cu_update_hal_rate_table()
1833 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92cu_update_hal_rate_table()
1836 if (ratr_value & 0x0000000c) in rtl92cu_update_hal_rate_table()
1837 ratr_value &= 0x0000000d; in rtl92cu_update_hal_rate_table()
1839 ratr_value &= 0x0000000f; in rtl92cu_update_hal_rate_table()
1842 ratr_value &= 0x00000FF5; in rtl92cu_update_hal_rate_table()
1848 ratr_value &= 0x0007F005; in rtl92cu_update_hal_rate_table()
1854 ratr_mask = 0x000ff005; in rtl92cu_update_hal_rate_table()
1856 ratr_mask = 0x0f0ff005; in rtl92cu_update_hal_rate_table()
1863 ratr_value &= 0x000ff0ff; in rtl92cu_update_hal_rate_table()
1865 ratr_value &= 0x0f0ff0ff; in rtl92cu_update_hal_rate_table()
1870 ratr_value &= 0x0FFFFFFF; in rtl92cu_update_hal_rate_table()
1875 ratr_value |= 0x10000000; in rtl92cu_update_hal_rate_table()
1878 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92cu_update_hal_rate_table()
1904 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; in rtl92cu_update_hal_rate_mask()
1907 1 : 0; in rtl92cu_update_hal_rate_mask()
1909 1 : 0; in rtl92cu_update_hal_rate_mask()
1910 enum wireless_mode wirelessmode = 0; in rtl92cu_update_hal_rate_mask()
1913 u8 macid = 0; in rtl92cu_update_hal_rate_mask()
1928 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92cu_update_hal_rate_mask()
1930 ratr_bitmap = 0xfff; in rtl92cu_update_hal_rate_mask()
1932 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92cu_update_hal_rate_mask()
1936 if (ratr_bitmap & 0x0000000c) in rtl92cu_update_hal_rate_mask()
1937 ratr_bitmap &= 0x0000000d; in rtl92cu_update_hal_rate_mask()
1939 ratr_bitmap &= 0x0000000f; in rtl92cu_update_hal_rate_mask()
1945 ratr_bitmap &= 0x00000f00; in rtl92cu_update_hal_rate_mask()
1947 ratr_bitmap &= 0x00000ff0; in rtl92cu_update_hal_rate_mask()
1949 ratr_bitmap &= 0x00000ff5; in rtl92cu_update_hal_rate_mask()
1953 ratr_bitmap &= 0x00000ff0; in rtl92cu_update_hal_rate_mask()
1961 ratr_bitmap &= 0x00070000; in rtl92cu_update_hal_rate_mask()
1963 ratr_bitmap &= 0x0007f000; in rtl92cu_update_hal_rate_mask()
1965 ratr_bitmap &= 0x0007f005; in rtl92cu_update_hal_rate_mask()
1971 ratr_bitmap &= 0x000f0000; in rtl92cu_update_hal_rate_mask()
1973 ratr_bitmap &= 0x000ff000; in rtl92cu_update_hal_rate_mask()
1975 ratr_bitmap &= 0x000ff015; in rtl92cu_update_hal_rate_mask()
1978 ratr_bitmap &= 0x000f0000; in rtl92cu_update_hal_rate_mask()
1980 ratr_bitmap &= 0x000ff000; in rtl92cu_update_hal_rate_mask()
1982 ratr_bitmap &= 0x000ff005; in rtl92cu_update_hal_rate_mask()
1987 ratr_bitmap &= 0x0f0f0000; in rtl92cu_update_hal_rate_mask()
1989 ratr_bitmap &= 0x0f0ff000; in rtl92cu_update_hal_rate_mask()
1991 ratr_bitmap &= 0x0f0ff015; in rtl92cu_update_hal_rate_mask()
1994 ratr_bitmap &= 0x0f0f0000; in rtl92cu_update_hal_rate_mask()
1996 ratr_bitmap &= 0x0f0ff000; in rtl92cu_update_hal_rate_mask()
1998 ratr_bitmap &= 0x0f0ff005; in rtl92cu_update_hal_rate_mask()
2006 if (macid == 0) in rtl92cu_update_hal_rate_mask()
2016 ratr_bitmap &= 0x000ff0ff; in rtl92cu_update_hal_rate_mask()
2018 ratr_bitmap &= 0x0f0ff0ff; in rtl92cu_update_hal_rate_mask()
2025 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | in rtl92cu_update_hal_rate_mask()
2027 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; in rtl92cu_update_hal_rate_mask()
2036 if (macid != 0) in rtl92cu_update_hal_rate_mask()
2061 sifs_timer = 0x0a0a; in rtl92cu_update_channel_access_setting()
2063 sifs_timer = 0x0e0e; in rtl92cu_update_channel_access_setting()
2072 u8 u1tmp = 0; in rtl92cu_gpio_radio_on_off_checking()
2074 unsigned long flag = 0; in rtl92cu_gpio_radio_on_off_checking()
2076 u8 usb_autosuspend = 0; in rtl92cu_gpio_radio_on_off_checking()
2097 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); in rtl92cu_gpio_radio_on_off_checking()
2141 * contrl reg at 0x1c. Then enable power down control bit in rtl92cu_gpio_radio_on_off_checking()
2142 * of register 0x04 BIT4 and BIT15 as 1. in rtl92cu_gpio_radio_on_off_checking()
2145 /* Enable register area 0x0-0xc. */ in rtl92cu_gpio_radio_on_off_checking()
2146 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); in rtl92cu_gpio_radio_on_off_checking()
2147 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); in rtl92cu_gpio_radio_on_off_checking()